Marantz SR8001 - Page 127

161
IC61 : CS4392KZZ
1. PIN DESCRIPTION - PCM DATA MODE
RST 1 Reset (Input) - Powers down device and resets all internal registers to their default settings.
VL 2 Logic Power (Input) - Positive power for the digital input/output.
SDATA 3 Serial Audio Data (Input) - Input for t wo’s complement serial audio data.
SCLK 4 Serial Clock (Input/Outpu t) - Serial clock for the serial audio interface.
LRCK 5 Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the
serial audio data line.
MCLK 6 Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters.
FILT+ 11 Positive Voltage Reference (Output) - Positive refer ence voltage for the internal sampling circuits.
CMOUT 12 Common Mode Voltage (Output) - Filter connect ion for internal quiescent voltage.
AMUTEC
BMUTEC
20
13
Mute Control (Output) - The Mute Control pin goes high during power-up i nitialization, reset, muting,
power-down or if the master clock to left/right clock frequency ratio is i ncorrect .
AOUTB-
AOUTB+
AOUTA+
AOUTA
14
15
18
19
Differential Analog Output (Outputs) - The full scale differential analog output level is specified in the
Analog Characteristics specificat ion table.
AGND 16 Ground (Input)
VA
17 Analog Power (Input) - Positive power for the analog section.
Control Port Mode Definitions
M3
7 Mode Selection (Input) - This pins should be tied to GND level during control port mode.
SCL/CCLK
8 Serial Control Port Clock (Input) - Serial clock for the serial control port.
SDA/CDIN 9 Serial Control Data (Input/Output) - SDA is a data I/O line in I
2
C mode. CDIN is the input data line for
the c ontrol port interface in SPI mode.
AD0/CS 10 Address Bit 0 (I
2
C) / Control Port Chip Select ( SPI) (Input/Output) - AD0 is a chip address pin in I
2
C
mode; CS
is the chip select signal for SPI format.
Stand-Alone Mode Definit ions
M3
M2
M1
M0
7
8
9
10
Mode Selection (Input) - Determines the operational mode of the device.
RST AMUTEC
VL AOUTA-
SDATA AOUTA+
SCLK VA
LRCK AG ND
MCLK AOUTB+
M3 AOUTB-
(SCL/CCLK) M2 BMUTEC
(SDA/CDIN) M1 CM OU T
(AD0/CS) M 0 F ILT+
1
2
3
4
20
19
18
17
5
6
7
8
16
15
14
13
9
10
12
11