58 Appendix B: Technical information
• Can perform horizontal or vertical flipping.
• Can subsample image data using nearest neighbor integer subsampling factors of
1 to 16.
• Has a Processing FPGA (only Pro Quad CXP-12) for on-board, custom
processing. Processing units (PUs) can be Matrox developed, or user developed
using the Vivado HSL tool of the Xilinx Vivado Design Suite and Matrox FPGA
Development Kit (FDK).
• Has 32 auxiliary signals (with the cable adapter bracket installed) that are path
independent. Each auxiliary I/O connector (HD-15) provides the following
number of signals:
- 3 TTL auxiliary I/O signals (trigger input or user input signals, or timer output,
re-routing of the CoaXPress trigger input, or user output signals).
- 1 LVDS auxiliary output signal (timer output, re-routing of the CoaXPress
trigger input, or user output signals).
- 2 LVDS auxiliary input signals (trigger input, rotary/linear encoder input, or
user input signals).
- 2 opto-isolated auxiliary input signals (trigger input signals).
Auxiliary input signals (or auxiliary I/O signals set to input) can be rerouted to
the CoaXPress trigger output signal and the auxiliary output signals.
The auxiliary input signals have interrupt generation capabilities. In addition,
when the LVDS auxiliary input signals are used for rotary/linear encoder input,
they can be debounced.
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