Figure 5-6. SAM E54 Xplained Pro EDBG Disconnect
Figure 5-7. SAM E54 Xplained Pro Current Measurement Headers
Related Links
Xplained Pro Power Header
Cortex Debug Connector
Connectors
5.6 Low-Power Mode
Acquiring the lowest power consumption of the device requires some specific settings of the GPIOs in
relation to the connected peripherals. The table below describes the settings needed for the lowest
possible power consumption. If not otherwise noted, all pins should disable all digital logic (DIR = 0, INEN
= 0 and PULLEN = 0).
Info: The power consumption on the miccrocontrollers VDD will be higher than specified in the
electrical characteristics of the device due to connected peripherals.
Table 5-30. Low Power Settings
SAM E54 pin Signal State Description
PC21 ETH RESET Output low The on-board Ethernet PHY KSZ8091 continuously
generates a 50 MHz clock signal to PA14 on the
SAM E54. When the KSZ8091 is in reset the clock
signal is not generated and the power consumption
of the SAM E54 is reduced.
SAM E54 Xplained Pro
© 2017 Microchip Technology Inc.
DS70005321A-page 38
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