Mitsubishi Electric Q06HCPU - Page 558

556
SD910
CPU module
data
backup/rest
oration
function
(backup
function)
Backup
function setting
Set the execution timing of automatic backup with bit pattern.
(OFF: Invalid, ON: Valid)
b0: Automatic backup setting by specification of day and
time
b1: Automatic backup setting by specification of time and
day of the week
b5: Upper limit status setting for the number of backup
data
*5
b10: Retry execution for the automatic backup
*5
b15: Setting for the automatic backup at occurrence of the
CPU stop error
(Multiple execution timings can be set.)
U
New
QnUDV
*4
SD912
Day and time
setting for
automatic
backup [day]
Set the day when an automatic backup by specification of
day and time is operated in BCD.
(1) Fixed to 00
(2) Day (1 to 31)
Example:On the 15th of each month, SD912 = 0015
H
SD913
Day and time
setting for
automatic
backup [hour
and minute]
Set the hour and minute when an automatic backup by
specification of the day and time is operated in BCD.
(1) Hour (0 to 23)
(2) Minute (0 to 59)
Example:For 8:30, SD913 = 0830
H
SD914
Time and day
of the week
setting for
automatic
backup [hour
and minute]
Set the hour and minute when an automatic backup by
specification of the time and day of the week is operated in
BCD.
(1) Hour (0 to 23)
(2) Minute (0 to 59)
Example:For 8:30, SD914 = 0830
H
SD915
Time and day
of the week
setting for
automatic
backup [day of
the week]
Set the day of the week when an automatic backup by
specification of the time and day of the week is operated in
the following bit pattern. (OFF: Invalid, ON: Valid)
b0: Sunday, b1: Monday, b2: Tuesday, b3: Wednesday, b4:
Thursday, b5: Friday, b6: Saturday
(Multiple setting can be set simultaneously)
SD916
Cause of error
occurred at
backup
This register stores the cause of an error that occurred
during backup.
0
H
: No error
Other than 0
H
: Error code (Page 411, Appendix 1.11)
("0" is stored at start of a backup of the CPU module.)
S (Error)
Number Name Meaning Explanation
Set by
(When Set)
Corresponding
ACPU
D9
Corresponding
CPU
b15 b10 b5 b0b1
(1) (2)
b15
b12
…
b11 b8…
b7 b4
…
b3 b0
…
(1) (2)
b15
b12
…
b11 b8…
b7 b4
…
b3 b0
…
(1) (2)
b15
b12
…
b11 b8…
b7 b4
…
b3 b0
…
b0b1b2b3b4b5b6