Motorola MTM700

Transceiver 800MHz (PCB No. 8486079Z01_O): SCHEMATICS, PCBs and PARTS LISTS MTM700 Mobile Radio / Detailed Service Manual 8.2.1 - 19
HDI_Controller 8466520A01_O (Sheet 1)
TMS
JTAG
RESET_IN
32.768 kHz Input
MCU_DE
EXP_UART_2
RESET_OUT
DCD
DSR
DTR
8-Wire RS232
DNP
RS232 ENABLE
NOTE: RESETS FROM THE BOTTOM CONNECTOR WILL ONLY BE POSSIBLE IF
Serial Audio Port Clock
DSP_SRD goes to CODEC/UCM/DGAN_Module
NU
Samsung 256k x16
SAP_TDMA Support for Digianswer Module
RX
TCK
Internal Pulldown
DSP_DE
CS2#-SRAM
MUX_CTRL =1 AND THE 8-WIRE INTERFACE IS THUS SET TO JTAG MODE
Unused GPO
SB9600
ESSI
INTERRUPT
RESET_OUTRESET_OUT
32.768 kHz Input
CTS
SCKA
SC2A
STDA
TX
RI
STDA TRST
Unused GPO
INT7
SC2A
TX_DETECT(SLUMP DETECT)
FR_GND
EB1#
ROW7
ROW6
INT5 - Option_Select_2
EXP_REQ (UART)
RTSRTS
RESET Low_Voltage_Dector
EXP_UART
INT2 - ON_OFF_CONTROL CH
LVFRACN+PCIC
ABACUS
SPIB
OE
ABACUS Frame SYNC
TX
NU
SAP
BBP
RX
TX
2 Meg x16
SYMBOL
ESSI
FLASH
INT1 - EXP_REQ
KEY_FAIL_OUT
NU
EXT_VPP
Gen Port Ctrl Reg (GPCR)
INT6
SPARE
DSP_STD goes to CODEC/UCM/DGAN_Module
17x17mm BGA
GPCR (Bit7)=0
SRDA
4-Wire RS232
GPCR = xxxxxxxx x00xxx00
GPCR (Bit7)=1
RESET_ABACUS
KEY_FAIL_IN
ADDAG Frame SYNC
REDCAP2
16.8 MHz Clock Output
16.8 MHz Input
Option_Select_2
RX
MUX_CTRL=0
Unused GPO Unused GPO
LAYER1 TIMER
STD Send Transmit I/Q Data to ADDAG
INT0 - PTT
WR_
SRDA
FR_GND
INT5 - Option_Select_2
FLASH SRAM RADIO SOFT TURN OFF
NU
RESET_OUT
Serial Audio Port Frame Sync CODEC Support
SRD Receive I/Q Data from ABACUS
EB0#
ADDAC
ODCT
INPUTS
SIM_CARD
RTS
CTS CTS
Gen Port Ctrl Reg (GPCR)
TDO
USE ONLY WITH NEXT GENRATION PATRIOT
ADDAG Serial Port Clock for Transmit Data
MOD
SBEP
DNP
16.8 MHz Input
INT4 - Option_Select_1
Unused GPO
DNP
ABACUS Serial Port Clock for Receive Data
Unused GPO
PIN NAME
MUX_CTRL=1
EXT- PTT
SCKA
PTT Option_Select_1
SPIA
TX
HW_ID
I/O
AUDIO_IN
SAP_TDMA Support for UCM
ESCORT
BUSY_OUT
BUSY_IN (IC2)
INT4 - Option_Select_1
TDI
GPCR = xxxxxxxx x11xxx11
RX
0
15
14
BGA128 BGA129
BGA154
BGA131 BGA137 BGA146 BGA126 BGA141 BGA142
TP0122
TP0120
TP0121
TP0119
1
TP0118
BGA145 TP0134 TP0135
TP0112
16
GND1
E8
GND2
F1
NC1
C4
VCC
F5
VCCQ
E1
VPP
A4
DQ7
F2
DQ8
D6
DQ9
E6
EN_CE
D7
EN_OE
F8
EN_RP
B4
EN_WE
B3
A5
EN_WP
DQ13
F3
DQ14
D2
DQ15
E2
DQ2
D5
DQ3
E5
DQ4
F4
D3
DQ5
DQ6
E3
A7
A7
A8
A3
A9
C3
DQ0
E7
DQ1
F7
DQ10
F6
DQ11
D4
DQ12
E4
A18
B5
A19
A6
A2
B8
C5
A20
A3
C7
A4
A8
A5
B7
A6
C6
A10
B2
A11
A2
A12
C2
A13
A1
A14
B1
A15
C1
A16
D1
A17
B6
U0102
28F320C3
A0
D8
A1
C8
BGA118
15
15
BGA144 BGA143
BGA107
6
14
TP0101
BGA112
BGA68
BGA70
BGA106
BGA122 BGA121 BGA127
BGA147
4
BGA130
BGA75
13
BGA109
BGA110
BGA111
R0104
47
NU
BGA140
0
R0108
BGA138
TP0124
TP0123
BGA51
BGA52
TP0117
BGA53
BGA22
D6
E1
VCC1
VSS
D1
E6
VSS1
IO9
B1
LB
A1
E3
NC1
NC2
G2
H1
NC3
NC4
H6
UB
B2
VCC
IO16
G1
C5
IO2
IO3
C6
D5
IO4
E5
IO5
IO6
F5
F6
IO7
IO8
G6
EN_WE
G5
IO1
B6
C1
IO10
IO11
C2
D2
IO12
E2
IO13
IO14
F2
F1
IO15
A7
D4
A8
H2
A9
H3
EN_CS
B5
EN_CS2
A6
EN_OE
A2
E4
A17
D3
A2
A5
A3
B3
B4
A4
A5
C3
A6
C4
A10
H4
A11
H5
A12
G3
A13
G4
A14
F3
A15
F4
A16
A0
A3
A1
A4
4
U0101
KM616FU4110
BGA86
BGA32
TP0115
TP0116
TP0113
TP0114
.01uF
8
5
C0103
BGA153
BGA150
11
5
BGA38
9
10
BGA108
5
BGA119
BGA77
BGA78
BGA82
BGA83
BGA84
BGA85
BGA71
4
BGA9
BGA93
BGA94
BGA45
BGA44
BGA43
BGA42
BGA41
9
10
11
BGA124
5
BGA156
BGA21
6
BGA20
BGA33
BGA16
BGA15
BGA14
BGA13
BGA95
BGA3
BGA4
BGA2
BGA135
BGA57
BGA134 BGA133 BGA132
11
9
BGA73
BGA74
3
4
6
BGA23
BGA79
BGA81
1
6
BGA58
BGA59
BGA60
11
BGA61
10
BGA46
BGA47
BGA48
BGA50
BGA49
NU
R0101
0
1
R0102
0
BGA30
6
BGA29
15
1
BGA19
11
BGA17
4
BGA91
BGA89
BGA88
8
6
2
1
12
2
13
7
BGA1
20
BGA80
20
XZYRW
C4
XYSEL
B5
XYST
B4
5
E0100
M5
XYD2
P8
XYD3
R8
XYD4
T8
XYD5
N8
XYD6
M6
XYD7 XYD8
L10
XYD9
M9
R7
XYD0
T7
XYD1 XYD10
M10
XYD11
M11
XYD12
N9
XYD13
T9
XYD14
R9
P9
XYD15
XYA2
B3
XYA3
B2
XYA4
A3
XYA5
A2
XYA6
A1
XYA7
C2 C3
XYA8
D1
XYA9 XYA0
A4
XYA1
D4 D2
XYA10
D3
XYA11
E2
XYA12
E1
XYA13
E3
XYA14 XYA15
E4
A6
TOUT5
D6
TOUT6
D7
TOUT7
TOUT8
C7
TOUT9
B7
H14
TRST
G15
TXA_TDO
TXB
K11
TOUT11
A8
TOUT12
D8
TOUT13
E6
TOUT14
E7
TOUT15
E8
D5
TOUT2
C6
TOUT3
B6
TOUT4
H13
TCK
G12
TDI
F12
TDO
G16
TEST
H12
TMS
A5
TOUT0
C5
TOUT1
TOUT10
B8
A9
SPI_CKA
SPI_CKB
D11
D13
SRDA
B14
SRDB
SRDB2
B12
D16
STDA
A14
STDB
T13
STO
E11
SPICS1A
SPICS1B
C10
E10
SPICS2A
SPICS2B
B10
E9
SPICS3A
SPICS3B
A10
F7
SPICS4A
SPICS4B
E12
P12
SENSE
N11
SIMCLK
N12
SIMDATA
T12
SIMRESET
F15
SIZ0
F14
SIZ1
D9
SPICS0A
SPICS0B
D10
B13
SC0B
A16
SC1A
A13
SC1B
A15
SC2A
C14
SC2B
C15
SCKA
C13
SCKB
SCKB2
A12
J16
ROW6_DCD_SC2A_DSP_DE
J13
ROW7_RI_SCKA_TCK
G13
RTSA_IC2A_RESET_IN
RTSB
K12
M2
RW
G14
RXA_IC1_TDI
RXB
J12
B16
SC0A
R13
RESET_IN
P13
RESET_OUT
L15
ROW0
K13
ROW1
K14
ROW2
K15
ROW3
J14
ROW4
J15
ROW5_IC2B
R10
PCAP
P10
PGND
E13
PSTAT0
E15
PSTAT1
D14
PSTAT2
D15
PSTAT3
T10
PVCC
T11
PWR_EN
B9
MISOA
MISOB
C11
R12
MOD
C9
MOSIA
MOSIB
D12
F16
MUX_CTL
M1
OE
N10
P1GND
N15
INT1
N14
INT2
M15
INT3
M16
INT4
M14
INT5
M13
INT6_DSR_STDA_TRST
L14
INT7_DTR_SCLK_SRDA_TMS
H11
MCU_DE
P4
D7
P5
D8
N5
D9
G11
DSP_DE
C12
DSP_IRQ
EB0
K1
J3
EB1
N16
INT0
N6
D13
N7
D14
P7
D15
T3
D2
R3
D3
P3
D4
T4
D5
R4
D6
R1
CS5
F13
CTSA_MCU_DE
CTSB
L12
T1
D0
T2
D1
P6
D10
R6
D11
T6
D12
P16
COLUMN5
P15
COLUMN6_OC1
P14
COLUMN7
N3
CS0
N2
CS1
P2
CS2
R2
CS3
P1
CS4
K2
CKIL
M3
CKO
L2
CKOH
N13
COLUMN0
R14
COLUMN1
R15
COLUMN2
T14
COLUMN3
R16
COLUMN4
L5
ADDR3
K6
ADDR4
J6
ADDR5
H6
ADDR6
G6
ADDR7
H5
ADDR8
G5
ADDR9
K4
CKIH
E5
ADDR15
G3
ADDR16
G4
ADDR17
F4
ADDR18
F1
ADDR19
J4
ADDR2
F2
ADDR20
F3
ADDR21
J2
ADDR0
J1
ADDR1
F5
ADDR10
H4
ADDR11
H1
ADDR12
H2
ADDR13
H3
ADDR14
3
U0100-1
30C40
22K
R0103
8
9
19
1
12
9
8
7
7
7
8
C0104
.01uF
.01uF
19
C0100
12
12
BGA18
1
3V
3
11
3
3
15
13
0
18
17
0
9
17
7
4
12
10
4
14
14
0.1uF
C0101
0
3V_FLTR
5
R0121
22K
5
18
5
14
C0105
4700pF
BGA12
3
3
BGA11
32
BGA5
BGA113
C0102
0.1uF
7
18
BGA64
BGA65
6
BGA66
21
1
10
BGA117
13
2V_FLTR
5
5
2
6
16
2
3V_FLTR
3
13
4
4
BGA6
BGA72
1
2
1
2
TP0133
3
14
BGA10
TP0132 TP0130 TP0131
BGA63
BGA56
BGA24
BGA25
BGA26
BGA27
BGA90
BGA115
BGA114
BGA67
BGA69
1
BGA76
4.7uF
16
2
C0106
13
BGA87
BGA37
15
8
4
3
4
BGA8
17
BGA7
12
10
1K
R0122
BGA116
BGA92
BGA62
BGA55
21
BGA54
3V_FLTR
BGA125
BGA28
BGA31
BGA40
2
BGA39
BGA36
2
BGA35 BGA34
BGA149
EEPOT_CS
SPARE3
EEPOT_TGL
SENSE
EEPOT_U_D
RESET_OUT
MOD
RS232_DTR
TX_DETECT
SOFT_TURN_OFF
SAP_STD
UCM_SAP_FSYNC
DGAN_SAP_FSYNC
AUDIO_ATTN_CTRL
PVCC
SPARE2
RS232_DSR
GP8_OUT_ACC14
SPIA_MOSI
SPIA_CLK
SPIA_CS0_ADD
SPIA_CS2_ODCT
SPIA_CS3_ESC
SPIA_CS4_ABA
SPIB_MOSI
SPIB_CLK
SPIB_CS1_UART
SPIB_CS2
HST_DATA(0:15)
PWM
RSB_CTS
MUX_CTRLC
AUD_PA_EN
Lock_FN
RSB_RTS
ADD_FSYNC
SSI_CLKOUT
MUX_CTRLA MUX_CTRLB
SRDB2
STO
AGC_2_IF
BAT_V_HIGHG
GP9_IN_ACC15
GP9_OUT_ACC15
SPARE1
GP8_IN_ACC14
ADD_TXE
16.8MHz_OUT
RSB_RX
SIM_POWER
SIM_RESET
SIM_CLOCK
ON_OFF_CONTROL
GP6_IN_ACC12
TOUT8
MEM_CNTL(6:1)
SPIB_MISO
SPIA_CS1_FN_PCIC
SIM_BUS(5:1)
RSB_TX
AGC_0_FE
TOUT_11
TOUT_13
AUDIO_SENSE
GP6_OUT_ACC12
RS232_RX
RS232_CTS
TOUT_15
LO_Driver_En
REF16.8_FN
GP2_OUT_ACC4
GP3_OUT_ACC6
GP3_IN_ACC6
GP4_IN_ACC9
GP5_IN_ACC10
SSI_SYNCB
RESET_ODCT_ADD
LV_DETECT
SAP_FSYNC
SIM_DATA
CS2_
EB1
EB0
SSI_DOUT
TEMP_SENSE
GP1_IN_ACC3
EXP_REQ
OPT_SEL_1
OPT_SEL_2
MUX_CTRL
RS232_DCD
RS232_RI
RS232_RTS
SSI_FSYNC
SAP_CLK ADD_TXCLK
SAP_SRD
ADD_STD
AGC_1_FE
PA_BIAS
PCIC_AD_SWTCH
ANT_EN
LO2_OUT
RS232_TX
HST_Addr(0:21)
SPIA_MISO
32KHz_CLK
ZWG0130877-O
AUDIO
CODEC
SMART CARD
BASEBAND
CODEC PORT
LAYER1 TIMER
CLOCK AND PLL
UART - A
UART - B
KEYPAD
INTERRUPTS
EMU AND DEBUG
JTAG AND TEST
EIM