MPC5746R Hardware Design Guide, Rev. 1
Power Supply
NXP Semiconductors12
voltages are in specification. LVD/HVD monitor limits are shown in Table 10 for your reference. Use the
latest MPC5746R Data Sheet for the final specification values. The device is held in reset regardless of
how slow the supply voltage rise is, until the point at which the POR and LVDs are released.
Table 10. Voltage monitor electrical characteristics
By default VDD_LV internal POR (POR085_c/POR098_c), internal core voltage monitor
(LVD_core_hot), VDD_HV_PMC voltage monitor (LVD_HV) and VDD_HV_IO_MAIN voltage
monitor (LVD_IO) are enabled. As shown in the mask option field under configuration column of the
Table 10, the user can enable/disable the voltage monitors of LVD/HVD by either of following methods.
1. Program the PMC_REE register directly by the application software. But, this method is only valid
for LVD_core_cold, HVD_core, HVD_HV and LVD_SAR configurations.
2. Program the PMC_REE_DCF_client DCF record into the UTEST area. With this option, the user
can disable the LVD_core_hot, enable the LVD_core_cold, HVD_core, HVD_HV and LVD_SAR
configurations. Note that the default configuration will remain active until the RGM enter phase 3,
where the UTEST configuration is read.
The POR and LVD circuits function correctly even if the input voltage is non-monotonic. A diagram
illustrating the on-chip LVD/HVD circuits is shown in Figure 5. For detailed information on the
low-voltage detect (LVD) and high-voltage detect (HVD) circuits, please refer to the MPC5746R
Reference Manual and Data Sheet.
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