NXP Semiconductors MPC5746R - Page 17

Power Supply
MPC5746R Hardware Design Guide, Rev. 1
NXP Semiconductors 17
3.7 Power sequence
The following section describes the power sequence and the relationship between the different supplies
during power-up and power-down.
The device is considered to be in a power sequence (or POWERUP state) when the power is not supplied
or is only partially powered. An internal power-on signal is used to identify the POWERUP state. This
signal is released high on exit of the power sequence. The power-on signal is a combination of certain
LVDs that are monitoring supplies:
6’b000101 hvd_flash reference 1.2 V
6’b000100 lvd_io divider tap point 1.97 V
6’b000011 lvd_io reference 1.2 V
6’b000010 Reserved —
6’b000001 Reserved —
6’b000000 Reserved —
6’b1111111 Reserved —
6’b111110 Reserved —
6’b111101 Reserved —
6’b111100 Reserved —
6’b111011 Reserved —
6’b111010 lvd_buddy reference 1.05 V
6’b111001 lvd_buddy sense 1.2 V (BD supply)
6’b111000 lvd_sar_adc divider tap point 2.25 V
6’b110111 lvd_sar_adc reference 1.2 V
6’b110110 hvd_sar_adc divider tap point 1.13 V
6’b110101 hvd_sar_adc reference 1.2 V
6’b110100
bandgap voltage with only curve
trimming
1.205 V
6’b110011 nwellbias regulator output 1.25 V
6’b110010 nwellbias regulator reference 1.25 V
6’b100100 ioseg3_sense VDD_HV_IO segment 3
6’b100011 ioseg2_sense VDD_HV_IO segment 2
6’b100010 vrefh_sd_adc 5 V
6’b100001 vrefh_sd_adc 5 V
6’b100000 vss_sd_adc 0 V
Table 11. ADC 0 Mux Interface
PMC_ADC_CS[ADC_CHSE] ADC Channel Output Typical Value