54
CJ1 and CJ1-H CPU Unit Comparison Section 1-6
Tex t
string,
table
data, and
data shift
instruc-
tions
Text string and table
data processing
instruction execution
Data processing can be
performed normally or in
the background (specified
for each instruction).
(Using time slices to pro-
cess instruction over sev-
eral cycles reduces the
effect of these instructions
on the cycle time.).
Data processing can be
performed normally or in
the background (specified
for each instruction).
(Using time slices to pro-
cess instruction over sev-
eral cycles reduces the
effect of these instructions
on the cycle time.).
Normal processing only.
Stack insertions/dele-
tions/replacements
and stack counts with
table processing
instructions
Supported.
Effective for tracking work-
pieces on conveyor lines.
Supported.
Effective for tracking work-
pieces on conveyor lines.
Not supported.
Data con-
trol
instruc-
tions
PID with autotuning Supported (eliminating the
need to adjust PID con-
stants).
Supported (eliminating the
need to adjust PID con-
stants).
Not supported.
Subrou-
tine
instruc-
tions
Global subroutines Supported (GSBS, GSBN,
and GRET instructions)
Enables easier structuring
of subroutines.
Supported (GSBS, GSBN,
and GRET instructions)
Enables easier structuring
of subroutines.
Not supported.
Failure
diagnosis
instruc-
tions
Error log storage for
FAL
Supported.
FAL can be executed with-
out placing an entry in the
error log. (Only system
FAL errors will be placed in
the error log.)
Supported.
FAL can be executed with-
out placing an entry in the
error log. (Only system
FAL errors will be placed in
the error log.)
Not supported.
Error simulation with
FAL/FALS
Supported.
Fatal and nonfatal errors
can be simulated in the
system to aid in debug-
ging.
Supported.
Fatal and nonfatal errors
can be simulated in the
system to aid in debug-
ging.
Not supported.
Data com-
parison
instruc-
tions
AREA RANGE COM-
PARE (ZCP) and
DOUBLE RANGE
COMPARE (ZCPL)
Supported. Supported. Not supported.
Index reg-
ister real
I/O
address
conver-
sion for
CVM1/CV
Program and real I/O
memory address com-
patibility with CVM1/
CV-series PLCs
CVM1/CV-series real I/O
memory addresses can be
converted to CJ-series
addresses and placed in
index registers or CJ-
series real I/O memory
addresses in index regis-
ters can be converted to
CVM1/CV-series
addresses.
CVM1/CV-series real I/O
memory addresses can be
converted to CJ-series
addresses and placed in
index registers or CJ-
series real I/O memory
addresses in index regis-
ters can be converted to
CVM1/CV-series
addresses.
Not supported.
Condition
Flag sav-
ing and
loading
Compatibility with
CVM1/CV-series
PLCs
Condition Flag status can
be saved or loading using
the SAVE CONDITION
FLAGS (CCS) and LOAD
CONDITION FLAGS
(CCL) instructions,
enabling applications
where Condition Flag sta-
tus must be passed
between different program
locations, tasks, or cycles.
Condition Flag status can
be saved or loading using
the SAVE CONDITION
FLAGS (CCS) and LOAD
CONDITION FLAGS
(CCL) instructions,
enabling applications
where Condition Flag sta-
tus must be passed
between different program
locations, tasks, or cycles.
Not supported.
Item CJ1-H CPU Unit
(CJ1H-CPU6@H)
CJ1M CPU Unit
(CJ1M-CPU@2/CPU@3)
CJ1 CPU Unit
(CJ1G-CPU4@)