Panasonic FPS Series

High-Speed Counter and Pulse Output
FPΣ User's Manual
108
Input mode Input signals
1
Inputs: X0+X1 (X3+X4)
2
Count
a
Increasing
b
Decreasing
Incremental/
decremental
1 2 3 2 30 3 24 1
TRUE
FALSE
TRUE
FALSE


a b a
b
34
1
Inputs: X0+X1 (X3+X4
or X4+X7)
2
Count
a
Increasing
b
Decreasing
Incremental/
decremental
control
3210 2 04 3 1


a
b
TRUE
FALSE
TRUE
FALSE
1
Inputs: X0 or X1 (X3 or
X4)
2
Reset input: X2 (X5)
3
Count
a
Rising edge: count
disabled, elapsed value
cleared
b
Falling edge: count
enabled
Count for reset
(incremental)
n-1 n
210 0
1 2
TRUE
FALSE
a
b


c

The reset is executed by the interruption at
a
(rising edge)
and
b
(falling edge)
The reset input can be enabled/disabled using bit 2 of
sys_wHscOrPulseControlCode (see page
111).
c
Count prohibited