Panasonic FPS Series

High-Speed Counter and Pulse Output
FPΣ User's Manual
112
Enabling/disabling counting operations (bit 1)
01 0
0
2
X0
1
t
X0 High-speed counter input
1
Elapsed value
2
Bit 1 of high-speed counter control code (count)
When bit 1 of the control code is set to TRUE, counting is prohibited and the elapsed value
keeps its current value. Counting is continued when bit 1 is reset to FALSE.
Resetting the elapsed value (software reset) of the high-speed counter to 0 (bit 0)
01
0
t
2
X0
1
X0 High-speed counter input
1
Elapsed value
2
Bit 0 of high-speed counter control code (software reset)
When bit 0 of the control code is set to TRUE, a software reset is performed and the elapsed
value is set to 0. The elapsed value keeps the value 0 until bit 0 is reset to FALSE.