Panasonic KX-FT21BX

CIRCUIT OPERATIONS
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KX-FT21LA
3-2. RESET CIRCUIT
The output from pin 1 of the Reset IC (IC4) resets the gate array (IC1).
(1) During a power surge, a positive reset pulse of 175 msec or more is generated and the system is reset completely.
This is done to prevent partial resetting and system runaway during a power fluctuation.
(2) When pin 1 of IC4 becomes low, it will prohibit the RAM (IC3) from changing data.
The RAM (IC3) will go into the backup mode, when it is backed up by a lithium battery.
Circuit Diagram
Timing Chart
(3) The watch dog timer, built-in the gate array (IC1), is initialized about every 1.5 ms.
When a watch dog error occurs, pin 18 of the gate array (IC1) becomes low.
The terminal of the WDERR signal is connected to the reset line so the WDERR signal works as the reset signal.
1
C30
4
2
R7
+5V
16
14
4
IC4
IC1
R6
18 17
XWDERR
XRESET1
XORESET
XRESET
XBACKEN
RESET
about 60 ms
4.2 4.0 4.0
0.8
4.2
0.8
+5
about 60 ms