25 CPU DATA (BASE UNIT)
25.1. IC8 (BBIC)
Pin No Description I/O Connection at Normal mode at Reset mode
1 INT1n/P1_1 D,O RLY O I-PU
2 VDDIO - - - -
3 VDD - - - -
4 VSS - - - -
5 SDA1/P2_5 D,I/O SDA I/O I
6 SCL1/P2_4 D,O SCL O I
7 INT5n/P1_5 D,O NC O-L I-PU
8 INT2n/P1[2] D,O P1[2]
9 AVD - - - -
10 AVS - - - -
11 CAP A,I CAP I I
12 Xtal1 A,I Xtal1 I -
13 VSSRF - - - -
14 RFCLKp A,I NC O Hi-Z
15 RSSI/RFCLKm A,I RSSI I Hi-Z
16 VDDRF - - - -
17 RFCLKd D,O RFCLKd O O-L
18 TDO A,O TDO O -
19 RDI D,I RDI I I
20 SK D,I/O SK - O-L
21 PD1/SIO D,I/O SIO - I-PD
22 LE D,I/O LE O O-H
23 P3[1]/PD1 D,I/O P3[1] O I-PD
24 P3[2]/PD2 D,I/O P3[2] O I-PD
25 P3[3]/PD3 D,I/O P3[3] O I-PD
26 P3[4]/PD4 D,I/O P3[4] O I-PD
27 TDOD/P3[5]/PD5 D,I/O P3[5] O I-PD
28 P3[6]/PD6 D,O NC O I-PD
29 VSS - - - -
30 VDDIO - - - -
31 VDD - - - -
32 PCM_FSC/INT0n/P1[0] D,I/O INT0n O I-PU
33 P0[0]/UTX D,I/O UTX O I-PU
34 P0[1]/URX D,I/O URX O I-PU
35 P0[2]/JTIO D,I/O JTIO O I-PU
36 P0[3]/SDA2 D,I/O P0[3] O I-PU
37 P0[4]/SCL2 D,I/O P0[4] O I-PU
38 P0[5]/SPICLK/PCM_CLK D,I/O SPICLK O I-PU
39 P0[6]/SPIDO/PCM_DOUT D,I/O SPIDO O I-PU
40 P0[7]/SPIDI/PCM_DIN D,I/O SPIDI O I-PU
41 VSS - - - -
42 VDD - - - -
43 P2[3]/ADC1 I ADC1 I I
44 P1[7]/CHARGE/INT7 I CHARGE I I-PD
45 RSTn I RSTn I I-PU
46 VBAT1 A,I VBAT1 I I
47 LDO1_CTRL D,O LDO1_CTRL O O-H
48 LDO2_CTRL D,O LDO2_CTRL O O-H
49 LDO1_Sense D,I LDO1_Sense I O-L
50 AVS2 - - -
51 AVD2 - - - -
52 CIDINn A,I CIDINn I I
53 LSRn/REF A,O REF O O
54 LSRp/REF A,O LSRp O O
55 RINGING A,I RINGING I I
56 MICn/CIDOUT A,I CIDOUT O O
57 VREFm - - - -
58 AGND A,O AGND O O
59 MICp A,I MICp I I
60 CIDINp A,I CIDINp I I
61 P1[4]/INT4n D,I/O P1[4] I I
62 PULSE_CTRL D,I/O Q12_ON I Q12_OFF
76
KX-TCD300FXS / KX-TCD300FXT / KX-TCA130FXS / KX-TCA130FXT