14.4. IC600 (M38B79MFA158) System Microprocessor
Pin No. Mark I/O Function
1 DECK2 I Tape mecha
condition input (Half2
/Reci_F/Mode/Reci_R)
2 KEY3 I Key 3 input
3 KEY2 I Key 2 input
4 KEY1 I Key 1 input
5
V_JOG_AD
I Volume jog A-D
detection input
6
J_JOG_AD
I EQ Joy jog A-D
detection input
7 CHG_AD1 I (Open Clamp) Chngr
sw A-D detection
input 1
8 CHG_AD2 I (Position/ bottom)
Chngr sw A-D
detection input 2
9 /CDRST O CD reset output
10 STATUS I CD signal processor
status input (INV)
11 SPE I Speana input
12 ST/DO/
SQCK
I/O Tuner if data/stereo
input and CD
subcode clock output
13 SD I/O Tuner signal detect
input
14 SUBQ I CD subcode data
input (INV)
15 RDS_CL I RDS clock input
16 RDS_DA I RDS data input
17 CNVSS - Flash mode terminal
(connect to ground)
18 /RESET - RESET input
19 XCOUT - 32.768 kHz sub clock
20 XCIN - 32.768 kHz sub clock
21 VSS - Ground (0V)
22 XIN - 4.19 MHz main clock
23 XOUT - 4.19 MHz main clock
24 VCC - Power supply (+5V)
25 MBP1 O MPU beat proof
output 1
26 MBP2 O MPU beat proof
output 2
27
MCLK/
PLLCK
O CD command clock
output/ tuner PLL
clock output
43
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