Panasonic TH-152UX1 - Block (6 of 23) Diagram

TH-152UX1
77
11.13. Block (6 of 23) Diagram
DN5
DN4
DN3
IN1
(P1)
IN2
(P3)
CNT
(P6)
HD-SDI
DVI
HD-SDI
DVI
4K INPUT
3D4/3D5
FAN B
OUTA
(P2)
P1 P9
P1
P4
FPGA
INPUT
FPGA
MEMORY
CONTROL
FPGA
OSD
V RATE
CONVERSION
LABELING
LVDS Tx
LVDS Tx
4K INPUT (UPPER)
4K FRONT END
FIFO
LVDS Tx
P6
FPGA
INPUT
LVDS Tx
P5
FPGA
V RESIZE
(2D)
LVDS Rx
LVDS Rx
2K INPUT
P7
LVDS OUTPUT (UPPER)
FRONT END POWER SUPPLY
FIFO
LVDS Rx
LVDS Tx
FAN A
PWR1
PWR2
PWR3
FRONT END EXTERIOR
LVDS OUTPUT (LOWER)
P1
P2P8
+5V
DCDC
+5V
DCDC
DCDC
DCDC
+12V
+5V
P12
P16
P2
P3
P10
P11
LVDS Rx
HD-SDI
HD-SDI
HD-SDI
HD-SDI
DVI
HD-SDI
DVI
4K INPUT
P1 P13
P2
FPGA
INPUT
P3
FPGA
MEMORY
CONTROL
P14
FPGA
OSD
V RATE
CONVERSION
LABELING
LVDS Tx
LVDS Tx
4K INPUT (LOWER)
FIFO
LVDS Rx
LVDS Tx
P15
LVDS Rx
HD-SDI
P5P2
SPLIT CONTROL
FPGA
FL8
FL7
FL6
FL5
FL9
+5V
+5V
+5V
+5V
+5V
+3.3V
DCDC
1.2V
DCDC
1.2V
+3.3V
1.2V
DCDC
+3.3V
1.2V
DCDC
+3.3V
1.2V
DCDC
+3.3V
1.2V
DCDC
+3.3V
2D4/2D5
4D4/4D5
1D4/1D5
OUTB
(P3)
OUTC
(P2)
OUTD
(P3)
from
1P6
from
4P6
from
3P6