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IRQ Assignment Conflicts
Most PCI devices can share an IRQ with another device, but they cannot use an IRQ simultaneously. To avoid
this type of conflict, see the documentation for each PCI device for specific IRQ requirements.
IRQ Line Assignment IRQ Line Assignment
IRQ0 System timer IRQ8 Real-time clock
IRQ1 Keyboard controller IRQ9 ACPI functions (used for power manage-
ment)
IRQ2 Interrupt controller 1 to enable IRQ8
through IRQ15
IRQ10 Available
IRQ3 Default for COM2 IRQ11 Available
IRQ4 Default for COM1 IRQ12 Available
IRQ5 Remote access controller IRQ13 Math coprocessor
IRQ6 Reserved IRQ14 IDE CD drive controller
IRQ7 Reserved IRQ15 Available
AMI POST Errors and Beep Codes
Test Points and Beep Codes
A checkpoint is either a byte or word value output to I/O port 80h. The BIOS outputs checkpoints throughout
bootblock and Power-On Self Test (POST) to indicate the task the system is currently executing. Checkpoints are
very useful in aiding software developers or technicians in debugging problems that occur during the pre-boot
process. Beep codes are used by the BIOS to indicate a serious or fatal error to the end user. Beep codes are used
when an error occurs before the system video has been initialized. Beep codes will be generated by the system
board speaker, commonly referred to as the “PC speaker.”
POST Code Checkpoints
The POST code checkpoints are the largest set of checkpoints during the BIOS pre-boot process. The following
table describes the type of checkpoints that may occur during the POST portion of the BIOS:
Checkpoint
Description
03 Disable NMI, Parity, video for EGA, and DMA controllers. Initialize BIOS, POST, Runtime
data area. Also initialize BIOS modules on POST entry and GPNV area. Initialized CMOS
as mentioned in the Kernel Variable "wCMOSFlags."
04 Check CMOS diagnostic byte to determine if battery power is OK and CMOS checksum is
OK. Verify CMOS checksum manually by reading storage area. If the CMOS checksum is
bad, update CMOS with power-on default values and clear passwords. Initialize status reg-
ister A. Initializes data variables that are based on CMOS setup questions. Initializes both
the 8259 compatible PICs in the system
05 Initializes the interrupt controlling hardware (generally PIC) and interrupt vector table.
06 Do R/W test to CH-2 count reg. Initialize CH-0 as system timer. Install the POSTINT1Ch
handler. Enable IRQ-0 in PIC for system timer interrupt. Traps INT1Ch vector to "POST-
INT1ChHandlerBlock."
08 Initializes the CPU. The BAT test is being done on KBC. Program the keyboard controller
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