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QUANTA QSSC-980 - Page 52

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錯誤
!
尚未定義樣式
— BIOS
36
Ratio Actual Value: Information only. Display the ratio at which processors currently run.
Hardware Prefetcher:[Enabled] [Disabled] This should be enabled in order to enable or disable the Hardware
Prefetcher Disable Feature. It is triggered by regular access patterns and helps predict future access, thereby over-
lapping memory latency with computation. By enabling concurrency between memory accesses and computation,
the computational benefit of higher processor frequencies is maximized.
Adjacent Cache Line Prefetch: [Enabled] [Disabled] This should be enabled in order to enable or disable the
Adjacent Cache Line Prefetch Disable Feature.The cache lines are fetched in pairs. This can be helpful if the data
to be used would continue to the next cache line, causing less cache misses to maximize throughput. When the da-
ta is not in adjacent lines, then performance can be slowed, since there will be more cache misses and more time
spent filling the cache lines
Max CPUID Value Limit: [Enabled] [Disabled] Disabled for Windows XP Intel processors from the Pentium
Pro onwards have a maximum CPUID input value of only 02h or 03h. The only exception is the Intel Pentium 4
with Hyper-Threading Technology (HTT). This is where the Max CPUID Value Limit BIOS feature comes in. It
allows you to circumvent problems with older operating systems that do not support the Intel Pentium 4 processor
with Hyper-Threading Technology. When enabled, the processor will limit the maximum CPUID input value to
03h when queried, even if the processor supports a higher CPUID input value.
Virtualization Tech: [Enabled] [Disabled] When enabled, a VMM can utilize the additional HW Caps. provided
by InteVirtualization Tech. Note: A full reset is required to change the setting. Designed to support multiple
software environments sharing same hardware resources, each software environment may consist of OS and ap-
plications.
Execute- Disable Bit Capability: [Enabled] [Disabled] When disabled, force the XD feature flag to always return
0. The Execute Disable Bit feature (XD bit) can prevent data pages from being used by malicious software to exe-
cute code. A processor with the XD bit feature can provide memory protection in either of the following modes:
Legacy protected mode if Physical Address Extension (PAE) enabled. Intel® 64 mode when 64-bit extension
technology is enabled.
Intel(R) HT Technology: [Enabled] [Disabled] When Disabled only one thread per enabled core is enabled. Intel
HT Technology is a processor design that combines hardware multithreading with superscalar processor technol-
ogy to allow multiple threads to issue instructions each cycle. SMT permits all thread contexts to simultaneously
compete for and share processor resources.
Active Processor Cores: [All] [1] [2] Number of cores to enable in each processor package.
Intel(R) SpeedStep(tm) tech: [Enabled] [Disabled] Intel® Xeon® processors support the Geyserville3 (GV3)
feature of the Enhanced Intel SpeedStep® technology. This feature changes the processor operating ratio and vol-
tage similar to the Thermal Monitor 1 (TM1) feature. It must be used in conjunction with the TM1. The BIOS
implements the GV3 feature in conjunction with the TM1 feature. This technology allows the clock speed of the
processor to be dynamically changed by software.
Intel(R) TurboMode tech: [Enabled] [Disabled] Turbo mode allows processor cores to run faster than marked
frequency in specific condition. Only for Nehalem processor The Turbo Mode feature allows extreme edition pro-
cessors to program thresholds for power/current which can increase platform performance by 10%.
Intel(R) CSTATE tech: [Enabled] [Disabled} CState: CPU idle is set to C2/C3/C4.
C3 State: [Enabled] [Disabled] Nehalem C state action select.
C6 State: [Enabled] [Disabled] Nehalem C state action select.
C7 State: [Enabled] [Disabled] Nehalem C state action select.

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