Quectel 5G Series User Manual

5G Module Series
5G EVB User Guide
5G_EVB_User_Guide 26 / 36
3.8. UART Interfaces (J2003/J2002)
The 5G EVB supports two UART interfaces: main UART J2003 and debug UART J2002.
The main UART interface is used for communication between the module and the host application.
The debug UART interface J2002 is used for Linux console and log output, and supports baud rate of
115200 bps (default).
The following figure shows a block diagram of UART interfaces of the EVB.
J0101
Module
Main UART
J2003
1.8V
U2001
RS232
Transceiver
3.3V/1.8V
Level Shift
Debug UART
J2002
RS232
U2002
1.8V
RS232
Transceiver
U2003
3.3V/1.8V
Level Shift
Q2001 Q2002
RS232
Figure 19: UART Block Diagram
3.9. PCIe to USB Interface (J1601)
The 5G EVB reserves a PCIe 3.0 signal over USB interface for developers’ testing, and this function is not
enabled by default. Please refer to the following block diagram.
J0101
Module
J1601
PCIe
Switch
U1501/U1701
CLK
TX0/1
RX0/1
WiFi
AP
USB3.0B
USB3.0 A<->B cable
SEL_1
SEL_2
Figure 20: PCIe Block Diagram

Quectel 5G Series Specifications

General

Brand	Quectel
Model	5G Series
Category	Control Unit
Language	English