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Quectel SG560D Series - Page 65

Quectel SG560D Series
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Smart Module Series
SG560D_Series_Hardware_Design 64 / 134
A reference circuit for SD card interface is shown below.
SD_CMD
120K
NM_51K
SD_DATA3
SD_DATA2
LDO18B_1V8
SD_CLK
SD_DATA0
SD_DET
SD_DATA1
P1-DAT2
P2-CD/DAT3
P3-CMD
P4-VDD
P5-CLK
P8-DAT1
GND
P6-VSS
P7-DAT0
DETECTIVE
GND
GND
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
SD_LDO9C
33R
33R
33R
33R
33R
33R
1K
33 pF
4.7 μF
SD_LDO6C
Module
R1
R2
R3 R4
R5
R6
NM_51K
NM_10K
NM_51K
NM_51K
R7
R8
R9
R10
R11
R12
R13
D1 D2
D3
D4 D5
D6
D7
D8
C1
C2
SD Card Connector
Figure 17: Reference Circuit for SD Card Interface
SD_LDO9C is a peripheral driver power supply for SD card. The maximum drive current is 600 mA.
Because of the high drive current, it is recommended that the trace width is 0.6 mm or above. To ensure
the stability of drive power, add a 4.7 μF and a 33 pF capacitor in parallel near the SD card connector.
SD_CMD, SD_CLK and SD_DATA[0:3] are all high speed signal traces. In PCB design, control the
characteristic impedance of them as 45 Ω, and do not cross them with other traces. It is recommended to
route these traces on the inner layer of PCB, and keep them of the same length. Additionally, SD_CLK
needs separate ground shielding.
Layout guidelines:
⚫ Control impedance to 45 Ω ±10 %, and add ground shielding.
⚫ The trace length difference between SD_CLK and SD_CMD/SD_DATA[0:3] should be less than
2 mm.
⚫ Trace length requirements: less than 150 mm for traces of 50 Mbps, less than 50 mm for traces of
140 Mbps.
⚫ The spacing between signal lines should be 1.5 times the line width.
⚫ The capacitive reactance of SD_DATA[0:3] traces should be less than 8 pF.
Table 17: SD Card Signal Trace Length Inside the Module
Pin No.
Signal
Length (mm)
188
SD_CLK
49.18

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