Quectel SG560D Series - Pcie Interface

Smart Module Series
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4.16. PCIe Interface
The module provides one PCIe interface, which supports 2-lane PCIe Gen 3 with data rate up to 8 Gbps.
Table 33: Pin Definition of PCIe Interface
Table 34: Trace Length of Differential Pairs Inside the Module
Pin Name
Pin No.
I/O
Description
Comment
PCIE1_REFCLK_P
594
AIO
PCIe1 reference clock (+)
Requires
differential
impedance of
85 Ω.
PCIE1_REFCLK_M
593
AIO
PCIe1 reference clock (-)
PCIE1_RX0_P
597
AI
PCIe1 recive 0 (+)
PCIE1_RX0_M
596
AI
PCIe1 recive 0 (-)
PCIE1_RX1_P
599
AI
PCIe1 recive 1 (+)
PCIE1_RX1_M
598
AI
PCIe1 recive 1 (-)
PCIE1_TX0_P
601
AO
PCIe1 transmit 0 (+)
PCIE1_TX0_M
600
AO
PCIe1 transmit 0 (-)
PCIE1_TX1_P
603
AO
PCIe1 transmit 1 (+)
PCIE1_TX1_M
602
AO
PCIe1 transmit 1 (-)
PCIE1_RST_N
605
DO
PCIe1 reset
1.8 V power
domain.
PCIE1_CLKREQ_N
606
DI
PCIe1 clock request
PCIE1_WAKE_N
607
DI
PCIe1 wake up
Pin No.
Signal
Length (mm)
Length Difference (P - M)
594
PCIE1_REFCLK_P
19.72
0.07
593
PCIE1_REFCLK_M
19.65
601
PCIE1_TX0_P
28.37
-0.02
600
PCIE1_TX0_M
28.39