Renesas RL78/G1D User Manual

RL78/G13 CHAPTER 6 TIMER ARRAY UNIT
R01UH0146EJ0100 Rev.1.00 356
Sep 22, 2011
Figure 6-19. Format of Noise Filter Enable Registers 1, 2 (NFEN1, NFEN2) (2/2)
Address: F0071H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
NFEN1 TNFEN07 TNFEN06 TNFEN05 TNFEN04 TNFEN03 TNFEN02 TNFEN01 TNFEN00
Address: F0072H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
NFEN2 TNFEN17 TNFEN16 TNFEN15 TNFEN14 TNFEN13 TNFEN12 TNFEN11 TNFEN10
TNFEN17 Enable/disable using noise filter of TI17/TO17/P106 pin input signal
0 Noise filter OFF
1 Noise filter ON
TNFEN16 Enable/disable using noise filter of TI16/TO16/P105 pin input signal
0 Noise filter OFF
1 Noise filter ON
TNFEN15 Enable/disable using noise filter of TI15/TO15/P104 pin input signal
0 Noise filter OFF
1 Noise filter ON
TNFEN14 Enable/disable using noise filter of TI14/TO14/P103 pin input signal
0 Noise filter OFF
1 Noise filter ON
TNFEN13 Enable/disable using noise filter of TI13/TO13/P67 pin input signal
0 Noise filter OFF
1 Noise filter ON
TNFEN12 Enable/disable using noise filter of TI12/TO12/P66 pin input signal
0 Noise filter OFF
1 Noise filter ON
TNFEN11 Enable/disable using noise filter of TI11/P11/P65 pin input signal
0 Noise filter OFF
1 Noise filter ON
TNFEN10 Enable/disable using noise filter of TI00/P64 pin input signal
0 Noise filter OFF
1 Noise filter ON
Remark The presence or absence of timer I/O pins of channel 0 to 7 depends on the product. See Table 6-2
Timer I/O Pins provided in Each Product for details.

Renesas RL78/G1D Specifications

General

Brand	Renesas
Model	RL78/G1D
Category	Computer Hardware
Language	English