RL78/G13 CHAPTER 6 TIMER ARRAY UNIT
R01UH0146EJ0100 Rev.1.00 405
Sep 22, 2011
Figure 6-59. Example of Set Contents of Registers to Delay Counter (1/2)
(a) Timer mode register mn (TMRmn)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TMRmn
CKSmn1
1/0
CKSmn0
1/0
0
CCSmn
0
M/S
Note
0/1
STSmn2
0
STSmn1
0
STSmn0
1
CISmn1
1/0
CISmn0
1/0
0
0
MDmn3
1
MDmn2
0
MDmn1
0
MDmn0
0
Operation mode of channel n
100B: One-count mode
Start trigger during operation
0: Trigger input is invalid.
1: Trigger input is valid.
Selection of TImn pin input edge
00B: Detects falling edge.
01B: Detects rising edge.
10B: Detects both edges.
11B: Setting prohibited
Start trigger selection
001B: Selects the TImn pin input valid edge.
Setting of MASTERmn or SPLITmn bit
0: Independent channel operation function.
(This is set to 1 when using channels 1 and 3 (TMRm1 and TMRm3) in the 8-bit
timer mode.)
Count clock selection
0: Selects operation clock (f
MCK).
Operation clock (f
MCK) selection
00B: Selects CKm0 as operation clock of channel n.
10B: Selects CKm1 as operation clock of channel n.
01B: Selects CKm2 as operation clock of channels 1, 3 (This can only be selected channels 1 and 3).
11B: Selects CKm3 as operation clock of channels 1, 3 (This can only be selected channels 1 and 3).
(b) Timer output register m (TOm)
Bit n
TOm
TOmn
0
0: Outputs 0 from TOmn.
(c) Timer output enable register m (TOEm)
Bit n
TOEm
TOEmn
0
0: Stops the TOmn output operation by counting operation.
Note TMRm2, TMRm4, TMRm6: MASTERmn bit
TMRm1, TMRm3: SPLITmn bit
TMRm0, TMRm5, TMRm7: Fixed to 0
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
<R>
<R>
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