Renesas RL78/G1D User Manual

RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT
R01UH0146EJ0100 Rev.1.00 541
Sep 22, 2011
Figure 12-1 shows the block diagram of the serial array unit 0.
Figure 12-1. Block Diagram of Serial Array Unit 0
PRS
013
4
PRS
003
PRS
012
PRS
011
PRS
010
PRS
002
PRS
001
PRS
000
4
f CLK
f CLK /2
0
to f CLK /2
11
f CLK /2
0
to f CLK /2
11
CKS00
MD001CCS00
STS00 MD002
SOE02SOE03
SOE01 SOE00
PM10
SAU0EN
SE03
SE02
SE01 SE00
ST03
ST02
ST01 ST00
SS03
SS02
SS01 SS00
TXE
00
RXE
00
DAP
00
CKP
00
EOC
00
PECT
00
OVCT
00
PTC
001
SLC
000
PTC
000
DIR
00
SLC
001
DLS
001
DLS
000
TSF
00
OVF
00
BFF
00
PEF
00
CK01
CK00
f MCK
f TCLK
f SCK
CK01
CK00
CK01
CK00
CK01
CK00
SNFEN
10
SNFEN
00
SNFEN00
SNFEN10
PM11 or P12
0
SOL02
0 SOL00
CKO02CKO03
CKO01 CKO00
SO02SO03
SO01 SO00
0
0
00
0
0
00
Serial output
enable register 0
(SOE0)
Serial channel
enable status
register 0 (SE0)
Serial channel
stop register 0
(ST0)
Serial channel
start register 0
(SS0)
Noise filter enable
register 0 (NFEN0)
SSEC0
SWC0
Serial standby
control register 0
(SSC0)
Serial output level
register 0 (SOL0)
Serial output register 0 (SO0)
Serial clock select register 0 (SPS0)
Selector
Selector
Peripheral enable
register 0 (PER0)
Prescaler
Shift register
Serial data register 00 (SDR00)
(Buffer register block)
(Clock division setting block)
Output latch
(P11 or P12)
Selector
Clock controller
Selector
Interrupt
controller
Output
controller
Communication controller
Serial flag clear trigger
register 00 (SIR00)
Communication
status
Error
information
Clear
Serial status register 00 (SSR00)
Error controller
Channel 0
Channel 1
Edge/level
detection
Serial communication operation setting register 00 (SCR00)
When UART0
Serial mode register 00 (SMR00)
Communication controller
Error controller
Edge/level
detection
Channel 2
Channel 3
Edge/level
detection
Communication controller
Communication controller
Error controller
When UART1
Output latch
(P10)
Mode selection
CSI00 or IIC00
or UART0
(for transmission)
Serial data output pin
(when CSI00: SO00)
(when IIC00: SDA00)
(when UART0: T
X D0)
Serial transfer end interrupt
(when CSI00: INTCSI00)
(when IIC00: INTIIC00)
(when UART0: INTST0)
Edge
detection
Serial clock I/O pin
(when CSI00: SCK00)
(when IIC00: SCL00)
Serial data input pin
(when CSI00: SI00)
(when IIC00: SDA00)
(when UART0: RxD0)
Serial transfer end interrupt
(when CSI01: INTCSI01)
(when IIC01: INTIIC01)
(when UART0: INTSR0)
Mode selection
CSI01 or IIC01
or UART0
(for reception)
Mode selection
CSI11 or IIC11
or UART1
(for reception)
Serial transfer error interrupt
(INTSRE0)
Serial data output pin
(when CSI01: SO01)
(when IIC01: SDA01)
Serial transfer end interrupt
(when CSI11: INTCSI11)
(when IIC11: INTIIC11)
(when UART1: INTSR1)
Serial transfer error interrupt
(INTSRE1)
Serial data output pin
(when CSI11: SO11)
(when IIC11: SDA11)
Serial data input pin
(when CSI01: SI01)
(when IIC01: SDA01)
Serial clock I/O pin
(when CSI01: SCK01)
(when IIC01: SCL01)
Selector
Serial data input pin
(when CSI10: SI10)
(when IIC10: SDA10)
(when UART1: R
X D1)
Mode selection
CSI10 or IIC10
or UART1
(for transmission)
Serial clock I/O pin
(when CSI10: SCK10)
(when IIC10: SCL10)
Serial data input pin
(when CSI11: SI11)
(when IIC11: SDA11)
Serial clock I/O pin
(when CSI11: SCK11)
(when IIC11: SCL11)
Noise
elimination
enabled/
disabled
Serial data output pin
(when CSI10: SO10)
(when IIC10: SDA10)
(when UART1: T
X D1)
Serial transfer end interrupt
(when CSI10: INTCSI10)
(when IIC10: INTIIC10)
(when UART1: INTST1)
Noise
elimination
enabled/
disabled
Synchro-
nous
circuit
Synchro-
nous
circuit
Edge/level
detection
Selector
Synchro-
nous
circuit
Synchro-
nous
circuit
Synchro-
nous
circuit

Renesas RL78/G1D Specifications

General

Brand	Renesas
Model	RL78/G1D
Category	Computer Hardware
Language	English