Renesas RL78/G1D User Manual

RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT
R01UH0146EJ0100 Rev.1.00 542
Sep 22, 2011
Figure 12-2 shows the block diagram of the serial array unit 1.
Figure 12-2. Block Diagram of Serial Array Unit 1
Serial clock select register 1 (SPS1)
PRS
113
4
PRS
103
PRS
112
PRS
111
PRS
110
PRS
102
PRS
101
PRS
100
4
f CLK
f CLK /2
0
to f CLK /2
11
Selector
f CLK /2
0
to
f
CLK /2
11
Selector
CKS10
MD101CCS10
MD102
Mode selection
CSI20 or IIC20
or UART2
(for transmission)
Communication controller
Shift register
Serial data register 10 (SDR10)
Interrupt
controller
SAU1EN
Peripheral enable
register 0 (PER0)
Serial data output pin
(when CSI20: SO20)
(when IIC20: SDA20)
(when UART2: TxD2)
Serial mode register 10 (SMR10)
(Buffer register block)
(Clock division setting block)
Error controller
TXE
10
RXE
10
DAP
10
CKP
10
Serial communication operation setting register 10 (SCR10)
EOC
10
PECT
10
Serial flag clear trigger
register 10 (SIR10)
OVCT
10
PTC
101
SLC
100
PTC
100
DIR
10
SLC
101
DLS
101
DLS
100
TSF
10
OVF
10
BFF
10
PEF
10
Serial status register 10 (SSR10)
Output
controller
Serial transfer end interrupt
(when CSI20: INTCSI20)
(when IIC20: INTIIC20)
(when UART2: INTST2)
Error
information
Channel 0
(LIN-bus supported)
CK11
CK10
fMCK
f TCLK
Communication controller
CK11
CK10
Edge
detection
Serial clock I/O pin
(when CSI20: SCK20)
(when IIC20: SCL20)
PM15
fSCK
Output latch
(P15)
Edge/level
detection
Serial data input pin
(when CSI20: SI20)
(when IIC20: SDA20)
(when UART2: RxD2)
Noise
elimination
enabled/
disabled
SNFEN20
SNFEN
30
Noise filter enable
register 0 (NFEN0)
SNFEN
20
When UART2
PM14 or PM13
Output latch
(
P14 or P13)
SOE10
Serial output
enable register 1
(SOE1)
SE11 SE10
Serial channel
enable status
register 1 (SE1)
ST11 ST10
Serial channel
stop register 1
(ST1)
SS11 SS10
Serial channel
start register 1
(SS1)
0
SOL10
SOE11
Serial output
level register 1
(SOL1)
Error controller
Selector
Clock controller
Selector
Communication
status
Prescaler
Serial output register 1 (SO1)
CKO10CKO11
SO11
SO10
0
0
00
0
0
00
Synchro-
nous
circuit
Synchro-
nous
circuit
Channel 1
(LIN-bus supported)
Serial data input pin
(when CSI21: SI21)
(when IIC21: SDA21)
Serial clock I/O pin
(when CSI21: SCK21)
(when IIC21: SCL21)
Selector
Synchro-
nous
circuit
Edge/level
detection
Mode selection
CSI21 or IIC21
or UART2
(for reception)
Serial transfer end interrupt
(when CSI21: INTCSI21)
(when IIC21: INTIIC21)
(when UART2: INTSR2)
Serial transfer error interrupt
(INTSRE2)
Serial data output pin
(when CSI21: SO21)
(when IIC21: SDA21)
SSEC1
SWC1
Serial standby
control register 1
(SSC1)
CK11
CK10
CK11
CK10
SNFEN30
Channel 2
Channel 3
Edge/level
detection
Communication controller
Communication controller
Error controller
When UART3
Mode selection
CSI31 or IIC31
or UART3
(for reception)
Serial transfer end interrupt
(when CSI31: INTCSI31)
(when IIC31: INTIIC31)
(when UART3: INTSR3)
Serial transfer error interrupt
(INTSRE3)
Serial data output pin
(when CSI31: SO31)
(when IIC31: SDA31)
Serial data input pin
(when CSI10: SI30)
(when IIC10: SDA30)
(when UART1: R
X D3)
Mode selection
CSI30 or IIC30
or UART3
(for transmission)
Serial clock I/O pin
(when CSI10: SCK30)
(when IIC10: SCL30)
Serial data input pin
(when CSI11: SI31)
(when IIC11: SDA31)
Serial clock I/O pin
(when CSI11: SCK31)
(when IIC11: SCL31)
Noise
elimination
enabled/
disabled
Serial data output pin
(when CSI30: SO30)
(when IIC30: SDA30)
(when UART3: T
X D3)
Serial transfer end interrupt
(when CSI30: INTCSI30)
(when IIC30: INTIIC30)
(when UART3: INTST3)
Edge/level
detection
Selector
Synchro-
nous
circuit
Synchro-
nous
circuit
SOE12
SE13 SE12
ST13 ST12
SS13 SS12
0
SOL12
SOE13
SO13
SO12
CKO12CKO13
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Renesas RL78/G1D Specifications

General

Brand	Renesas
Model	RL78/G1D
Category	Computer Hardware
Language	English