Renesas RL78/G1D User Manual

RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT
R01UH0146EJ0100 Rev.1.00 595
Sep 22, 2011
Figure 12-41. Flowchart of Master Reception (in Continuous Reception Mode)
Starting CSI communication
Reading receive data to SIOp
(=SDRmn[7:0])
Write STmn bit to 1
=
1
No
End of communication
Clear MDmn0 bit to 0
Communication continued?
Yes
Clear SAUmEN bit of the
PER0 register to 0
Writing dummy data to
SIOp (=SDRmn[7:0])
<2>
<3>
<5>
<6>
<7>
<4>
<8>
No
Yes
BFFmn = 1?
For the initial setting, refer to Figure 12-35.
(Select
buffer empty interrupt)
SAU default setting
Setting receive data
Setting storage area of the receive data, number of communication data
(Storage area, Reception data pointer, Number of communication data and
Communication end flag are optionally set on the internal RAM by the software)
Wait for receive completes
Buffer empty/transfer end interrupt
≥ 2
Number of communication
data?
Writing to SIOp makes SCKp
signals out (communication starts)
When interrupt is generated, it moves to
interrupt processing routine
Subtract -1 from number of
transmit data
<1>
Read receive data, if any, then write them to storage
area, and update receive data pointer (also subtract -1
from number of transmit data)
Writing dummy data to
SIOp (=SDRmn[7:0])
= 0
<2>
RETI
No
Number of communication
data = 0?
Yes
When number of communication data
becomes 0, receive completes
Enables interrupt
Clear interrupt request flag (XXIF), reset interrupt mask (XXMK) and set
interrupt enable (EI)
Write MDmn0 bit to 1
Disable interrupt (MASK)
Main routine Main routineInterrupt processing routine
Remark <1> to <8> in the figure correspond to <1> to <8> in Figure 12-40 Timing Chart of Master Reception
(in Continuous Reception Mode).
<R>

Renesas RL78/G1D Specifications

General

Brand	Renesas
Model	RL78/G1D
Category	Computer Hardware
Language	English