Renesas RL78/G1D User Manual

RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA
R01UH0146EJ0100 Rev.1.00 745
Sep 22, 2011
Figure 13-29. Master Operation in Multi-Master System (3/3)
Writing IICA0
WTIM0 = 1
WREL0 = 1
Reading IICA0
ACKE0 = 1
WTIM0 = 0
WTIM0 = WREL0 = 1
ACKE0 = 00
Writing IICA0
Yes
TRC0 = 1?
Restart?
MSTS0 = 1?
Starts communication
(specifies an address and transfer direction).
Starts transmission.
No
Yes
Waits for data reception.
Starts reception.
Yes
No
INTIICA0
interrupt occurs?
Yes
No
Transfer end?
Waits for detection of ACK.
Yes
No
INTIICA0
interrupt occurs?
Waits for data transmission.
Does not participate
in communication.
Yes
No
INTIICA0
interrupt occurs?
No
Yes
ACKD0 = 1?
No
Yes
No
C
2
Yes
MSTS0 = 1?
No
Yes
Transfer end?
No
Yes
ACKD0 = 1?
No
2
Yes
MSTS0 = 1?
No
2
Waits for detection of ACK.
Yes
No
INTIICA0
interrupt occurs?
Yes
MSTS0 = 1?
No
C
2
Yes
EXC0 = 1 or COI0 = 1?
No
1
2
SPT0 = 1
STT0 = 1
Slave operation
END
Communication processingCommunication processing
Remarks 1. Conform to the specifications of the product that is communicating, with respect to the transmission and
reception formats.
2. To use the device as a master in a multi-master system, read the MSTS0 bit each time interrupt INTIICA0
has occurred to check the arbitration result.
3. To use the device as a slave in a multi-master system, check the status by using the IICA status register
0 (IICS0) and IICA flag register 0 (IICF0) each time interrupt INTIICA0 has occurred, and determine the
processing to be performed next.

Renesas RL78/G1D Specifications

General

Brand	Renesas
Model	RL78/G1D
Category	Computer Hardware
Language	English