RL78/G13 CHAPTER 18 STANDBY FUNCTION
R01UH0146EJ0100 Rev.1.00 856
Sep 22, 2011
(2) Oscillation stabilization time select register (OSTS)
This register is used to select the X1 clock oscillation stabilization wait time when the STOP mode is released.
When the X1 clock is selected as the CPU clock, the operation waits for the time set using the OSTS register after the
STOP mode is released.
When the high-speed on-chip oscillator clock is selected as the CPU clock, confirm with the oscillation stabilization
time counter status register (OSTC) that the desired oscillation stabilization time has elapsed after the STOP mode is
released. The oscillation stabilization time can be checked up to the time set using the OSTC register.
The OSTS register can be set by an 8-bit memory manipulation instruction.
Reset signal generation sets this register to 07H.
Figure 18-2. Format of Oscillation Stabilization Time Select Register (OSTS)
Address: FFFA3H After reset: 07H R/W
Symbol 7 6 5 4 3 2 1 0
OSTS 0 0 0 0 0 OSTS2 OSTS1 OSTS0
Oscillation stabilization time selection
OSTS2 OSTS1 OSTS0
fX = 10 MHz fX = 20 MHz
0 0 0 2
8
/fX 25.6
μ
s 12.8
μ
s
0 0 1 2
9
/fX 51.2
μ
s 25.6
μ
s
0 1 0 2
10
/fX 102.4
μ
s 51.2
μ
s
0 1 1 2
11
/fX 204.8
μ
s 102.4
μ
s
1 0 0 2
13
/fX 819.2
μ
s 409.6
μ
s
1 0 1 2
15
/fX 3.27 ms 1.64 ms
1 1 0 2
17
/fX 13.11 ms 6.55 ms
1 1 1 2
18
/fX 26.21 ms 13.11 ms
Cautions 1. To set the STOP mode when the X1 clock is used as the CPU clock, set the OSTS register before
executing the STOP instruction.
2. Before changing the setting of the OSTS register, confirm that the count operation of the OSTC
register is completed.
3. Do not change the value of the OSTS register during the X1 clock oscillation stabilization time.
4. The oscillation stabilization time counter counts up to the oscillation stabilization time set by
the OSTS register. If the STOP mode is entered and then released while the high-speed on-chip
oscillator clock is being used as the CPU clock, set the oscillation stabilization time as follows.
• Desired OSTC register oscillation stabilization time ≤ Oscillation stabilization time set by
OSTS register
Note, therefore, that only the status up to the oscillation stabilization time set by the OSTS
register is set to the OSTC register after STOP mode is released.
5. The X1 clock oscillation stabilization wait time does not include the time until clock oscillation
starts (“a” below).
STOP mode release
X1 pin voltage
waveform
a
Remark f
X: X1 clock oscillation frequency
To Next Page
Loading...
Need help?
General
