RL78/G13 CHAPTER 19 RESET FUNCTION
R01UH0146EJ0100 Rev.1.00 877
Sep 22, 2011
Table 19-2. Hardware Statuses After Reset Acknowledgment (4/4)
Hardware
Status After Reset
Acknowledgment
Note 1
Reset function Reset control flag register (RESF) Undefined
Note 2
Voltage detection register (LVIM) 00H
Note 2
Voltage detector
Voltage detection level register (LVIS) 00H/01H/81H
Notes 2, 3
SFR address registers 0 to 3 (DSA0 to DSA3) 00H
RAM address registers 0 to 3 (DRA0 to DRA3) 0000H
Byte count registers 0 to 3 (DBC0 to DBC3) 0000H
Mode control registers 0 to 3 (DMC0 to DMC3) 00H
DMA controller
Operation control registers 0 to 3 (DRC0 to DRC3) 00H
Request flag registers 0L, 0H, 1L, 1H, 2L, 2H, 3L (IF0L, IF0H, IF1L,
IF1H, IF2L, IF2H, IF3L)
00H
Mask flag registers 0L, 0H, 1L, 1H, 2L, 2H, 3L (MK0L, MK0H, MK1L,
MK1H, MK2L, MK2H, MK3L)
FFH
Priority specification flag registers 00L, 00H, 01L, 01H, 02L, 02H, 03L,
10L, 10H, 11L, 11H, 12L, 12H, 13L (PR00L, PR00H, PR01L, PR01H,
PR10L, PR10H, PR11L, PR11H, PR02L, PR02H, PR12L, PR12H,
PR03L, PR13L)
FFH
External interrupt rising edge enable registers 0, 1 (EGP0, EGP1) 00H
Interrupt
External interrupt falling edge enable registers 0, 1 (EGN0, EGN1) 00H
Flash memory CRC control register (CRC0CTL) 00H
Flash memory CRC operation result register (PGCRCL) 0000H
CRC input register (CCRIN) 00H
CRC data register (CRCD) 0000H
Invalid memory access detection control register (IAWCTL) 00H
Safety functions
RAM parity error control register (RPECTL) 00H
Flash memory Data flash control register (DFLCTL) 00H
BCD correction circuit BCD correction result register (BCDAJ) Undefined
(Notes and Remark are listed on the next page.)
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