-
MZ-5600
Channel 0 of
the
lBOCTC
is
used
in
the
timer mode,
and its
output
(lC/TOO): Pulse with a
13J,tS
period)
is
applied
to
the
Data Request DREQ2 pin
of
the
8237
(DMA controller)
via
a type-D
F/F
as
a refresh request
signal. When receiving a DREQ2 signal,
the
8237
outputs
a Data Acknowledgement DACK2
to
place
itself
in
the
DMA
mode (see
DMA
interface)_
5-5 Memory protection logic (MPL)
LUsed
only SEEG]
Specification
1. Addresses protected
The
IPL
ROM,
VRAM, vector RAM, and bank 1 are not
protected.
7FFFFH~------~~
Protected
800HIr---------f-L.
Since
the
bank 1
is
for memory protection by itself,
the
protect
function does
not
cover this area.
2. Task register
Since
MPL
is
capable
of
managing four tasks, choice
of
task
must be done
in
the
following manner:
I/O address
60H
(Write only)
03
02
01
DO
I I I I I
I
IL.-----Task
0
'-------Task
1
L------Task
2
'--------------Task
3
EX)
0001
~
Task 0
in
execution
01
00
~
Task 1
in
execution
3.
Protection memory
Depending
on
the
nature of
the
task, read and write
to
the
task
is
limited.
Memory address
BANK1
800H -
7FFFFH
-26-
03
02
01
DO
I I I I I
l
'----Task 0
'------Task
1
'-------Task
2
'--------------
Task 3
EX)
11
01
~
Only
the
task 0
is
applicable
0011
~
Tasks 2 and 3 are applicable
Location
CPUPWB
MPL
MZ-1R22
II~
Memory
map
Bank 7
FFFFFH
V-RAM
COOOOH
AOOOOH
zao
SOOOOH
System
RAM
OOOOOH
16
bit
r
MPL
Memory
ProtectIon
l...ogIc
Bank 1
Protection
memory
..,.--..,7
F F F F H
-t---tSOOH
~
To Next Page
Loading...
Need help?
General
