Block Diagram
of
Memory Protection
ADO
l
AD19
8088
CPU
NUl
COMMAND
8237
DMAC
r-
______________
~ADD
CAS
RAS
SYSTEM
RAM
(S12KB)
CRTL
I-----......ct
>-----'
-
MZ-5600
DD
~--r-r-----------,n
~~~~n
r7----RESET
SW
L..-
________
-{
-...Jp---Timer
MPL
operation
When
four tasks are operated simultaneously in
the
time
shared mode, every task
is
allocated
to
the
system
RAM
area (512
KB,
max.).
If
a task should
try
to
access
the
system
RAM
beyond
the
limit,
not
only
the
RAM
is pro-
tected, but also
the
condition
is
sensed and informed
to
the
CPU
with
NMI.
Since the currently operating task is
set
in
the
task
register
(output on
ilo address
60H),
the
task information should
be
set by
the
OS
each time
the
task changes.
One word (4 bits)
of
the
protection memory corresponds
to
one kilobytes
of
the system
RAM,
which
is
used
to
indicate
the system
RAM
area
the
task can
access.
To
enable
the
use
of
the
1
KB
area
of
54400H through
547FFH
for
the
tasks
1 and 2 and
to
disable tasks 0 and
3,
for
instance.
"1001"
has
to
be set
in
the
protect memory.
MPL
does
not
func-
tion
at
power on and when
"0"
is
set in
the
task register.
Shown next
is
the
procedure
to
set
up
the
protection
memory area.
Theory
of
memory protection
For instance,
the
protection
RAM
area 10000H
of
the
bank
1 contains
"1010"
to
enable
the
1
KB
area
of
the
system
RAM
1000H - 103FFH for access by tasks 0
and
2.
If
the
system
RAM
area
of
1000H -
103FFH
is tried
to
-~-
RAM
C1K
x4)
I/O
Task 3
~ection
Logic
read
or
write during
the
execution
of
the task 1 with
"0010"
in
the
task register,
the
data
"1010"
is
sent from
the
protection
RAM.
Then,
the
protection data
"1010"
is
Ored
with
"0010"
of
the
task register by
the
protection
logic. Since
the
result would not be
"0000"
but
"0010",
it
prohibits
CAS signal from
the
system
RAM.
For the
dynamic RAM.
the
same cycle
as
the
RAS
only fresh
is
executed. which in consequence disables
to
read or write
to
the
RAM.
At
the
same time,
the
NMI
is
issued
to
the
CPU
with
the
CAS inhibit signal.
The reason why CAS
is
prohibited for protection
of
the
memory
is
that
it
is
not
practically possible
to
use a
high
speed
protection
RAM
and
the
protection logic which are
required
to
disable
the
read
or
write command using the
address information.
WAVEFORMS
·1:
The protection data are sampled
at
a high
to
low transi·
tion
of
the
command and
the
contents of the task
register
is
operated and CASINH
is
forced active
if
required. CAS would
not
go active
as
long
as
CASINH
is active.
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