(5)
Video RAM configuration
The
VRAM consists
of
dynamic RAM chips
of
16K x 4
bits (8KB)
each.
Its memory map
is
shown below.
The
VRAM
can
be
accessed
from both the
CPU
and
the
graphic
display controller (GDC).
The
CPU
accesses
it
byte-by-byte
(8
bits) or word-by-word (16 bits),
while the GDC
accesses
it
word-by-word only.
CPU
i
I
GDC
i
i
1
uni
t = 8
bi
t
: Optional
VRAM
3(32KBII
lunit=lSbit
~
t
aK{
Byte
...
RAIl
E8000H
EOOOOH
D8000H
roOOOH
C8000H
COOOOH
IIPXER
I
I
I
14000H
VRAM
3
(32KB)
lOOOOH
I
I.
I
IOptional
VRAM
2(32KB)1
I
OCOOOH
VRAM
2 (32KB)
I
08000H
I
I
I Optional
VRAM
1
(32KBIt
I I
I
,
04000H}
VRAM
1 (32KB)
OOOOOH
Fig. 65
•
EG,.FILE
I I I I
I I I "
, "
i
16KW
: i "
Fig. 66
14·2 Display interface logic description
Display
interface logic configuration
lSK
Word
The
display interface consists
of.
the following chips
and
blocks:
*
Graphic
display controller (GDC):
* Window controller (WDC):
* Video display controller 1 (VDC1):
JLPD7220
LZ90E07
SP61
02-035
* Video display controller 2 (VDC2):
SP61
02-034
• * VRAM:
Dynamic RAM
Static RAM
lIP
*
Mapping
RAM
(1
K x 4 bits):
*
Palette
register file:
74
LS670
*
Bus
buffers
and
other
TTL
gates
The
display control logic block diagram
is
shown in Fig. 66.
The
display control logic consists
of
a GDC, WDC, timing
-55-
-
MZ-5600
generators (VDC1), video
signal
controller (VDC2),
and
VRAM.
Each
block
can
be
accessed
from both the
CPU
and
GDC
since
the display cycle
is
divided into a
CPU
cycle
and
a GDCcycle.
While
the
CPU
treats the GDC
as
one
of
the
I/O
devices,
the
GDC functions
as
a sub-processor within the display control
logic.
14·3 Logic description
(1) Graphic display controller (GDC:
JLPD7220)
The
GDC
is
an
integral graphic display controller
used
to
control
text
and
graphic information display on a
raster
scan
display
screen.
It
has
the following features:
1) Functions
and
features
* Sync.
signal
generation: Constantly
generates
a
sync.
signal
and
controls display
and
drawing
timing.
" Preparations
for
drawing: Calculates drawing ad·
dresses
based
on given command parameters.
* Execution
of
drawing: Outputs
address
information
to
the
VRAM
to
update or correct
VRAM
data.
* Display: Constantly calculates display
addresses
and transfers them
to
the VRAM
to
read
display data.
*
Capable
of
high-speed graphic drawing.
* Direct
VRAM
control capability.
* Built-in F I
FO
for
I/O
interface with the
CPU.
* Part
of
the VRAM
area
can
be
displayed.
* Vertical
and
horizontal scrolling
is
easy
.
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