Siemens IM 151-7 - Page 16

Contents
xvi
ET 200S IM 151-7 CPU Interface Module
A5E00058783-04
Tables
1-1 Limitations in the use of ET 200S modules 1-2. . . . . . . . . . . . . . . . . . . . . . . . . .
1-2 Topics of the manuals in the ET 200S manual package 1-7. . . . . . . . . . . . . . .
3-1 Addresses of the ET 200S I/O modules 3-3. . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-2 Accessing the address areas 3-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-3 Addressing interface in STEP 7 V5.1 (extract) 3-8. . . . . . . . . . . . . . . . . . . . . . .
4-1 Behavior of the IM 151-7 CPU depending on the DP interface setting 4-4. . .
4-2 Network components 4-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6-1 Event recognition of the IM 151-7 CPU as a DP master 6-5. . . . . . . . . . . . . . .
7-1 Configuration options 7-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-2 Ways to reset the memory 7-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-3 Internal CPU events at memory resetting 7-5. . . . . . . . . . . . . . . . . . . . . . . . . . .
7-4 LED display for PROFIBUS-DP (IM 151-7 CPU is an I slave) 7-10. . . . . . . . . .
7-5 LED display for PROFIBUS-DP (IM 151-7 CPU is a master) 7-11. . . . . . . . . .
7-6 Responses to operating mode changes and interruptions in user data
transfer in the DP master and the ET 200S with the IM 151-7 CPU
as an I slave 7-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-7 Evaluation of RUN-STOP transitions in the DP master/ ET 200S with
IM 151-7 CPU as the I slave 7-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-8 Structure of station status 1 (byte 0) 7-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-9 Structure of station status 2 (byte 1) 7-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-10 Structure of station status 3 (byte 2) 7-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-11 Structure of the master PROFIBUS address (byte 3) 7-18. . . . . . . . . . . . . . . . .
7-12 Structure of the manufacturer identification (bytes 4 and 5) 7-18. . . . . . . . . . . .
7-13 Identifiers of the module classes 7-27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-1 Attributes from the device database (DDB) file 8-2. . . . . . . . . . . . . . . . . . . . . .
8-2 Positions of the mode selector 8-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-3 LEDs for CPU functionality 8-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-4 Available MMCs 8-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-5 Firmware update with MMC 8-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-6 Backing up the operating system 8-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-7 Retentive behavior of the memory objects 8-14. . . . . . . . . . . . . . . . . . . . . . . . . .
8-8 Retentive behavior of the DBs in IM 151-7 CPU 8-14. . . . . . . . . . . . . . . . . . . . .
8-9 Address areas of the system memory 8-20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-10 Connecdevices 8-27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-11 Features of the clock 8-28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-12 Distribution of the S7 connections 8-32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-13 Availability of the S7 connections 8-33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-14 Communication utilities of the IM 151-7 CPU 8-34. . . . . . . . . . . . . . . . . . . . . . . .
8-15 GD resources of the IM 151-7 CPU 8-37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-16 Overview of the blocks 8-42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-17 Parameter blocks, setparameters and their ranges for the
IM 151-7 CPU 8-44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-18 Parameterization of the reference junction 8-46. . . . . . . . . . . . . . . . . . . . . . . . . .
8-19 Result of the preset/actual comparison in modules that cannot be
parameterized 8-49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-20 Result of the preset/actual comparison in the case of parameterizable
modules with the power module switched on 8-49. . . . . . . . . . . . . . . . . . . . . . . .
8-21 Result of the preset/actual comparison in the case of parameterizable
modules with the power module switched off 8-50. . . . . . . . . . . . . . . . . . . . . . . .
9-1 Operating system processing time in the scan cycle checkpoint 9-3. . . . . . . .
9-2 Process image updating 9-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9-3 Dependency of the user program scanning time 9-4. . . . . . . . . . . . . . . . . . . . .
9-4 Extending the cycle by nesting interrupts 9-4. . . . . . . . . . . . . . . . . . . . . . . . . . .
9-5 Interrupt response times of the IM 151-7 CPU (without communication) 9-8.