System and operating states of the S7–400H
11.1 Introduction
S7-400H
System Manual, 03/2012, A5E00267695-11
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Continued bumpless operation even if redundancy of a CPU is lost
The event-driven synchronization method ensures bumpless continuation of operation by the
reserve CPU even if the master CPU fails.
Self-test
Malfunctions or errors must be detected, localized and reported as quickly as possible.
Consequently, extensive self-test functions have been implemented in the S7-400H that run
automatically and entirely in the background.
The following components and functions are tested:
● Coupling of the central racks
● Processor
● Internal memory of the CPU
● I/O bus
If the self-test detects an error, the fault-tolerant system tries to eliminate it or to suppress its
effects.
For detailed information on the self-test, refer to section Self-test (Page 137).
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