2 Functions
152
7UT613/63x Manual
C53000-G1176-C160-2
Figure 2-66 Logic diagram of the high-set stages I>> for residual current (simplified)
Each phase current and the zero sequence current 3·I0 are, additionally, compared
with the setting value I> (common setting for the three phase currents) and 3I0> (in-
dependent setting for 3·I0). If inrush restraint is used, a frequency analysis is per-
formed first. Depending on the detection of inrush currents, either normal pickup an-
nunciations or relevant inrush messages are issued. After user-configured delay times
T I> or T 3I0> have elapsed, a trip signal is issued assuming that no inrush current
is detected or inrush restraint is disabled. If inrush restraint is enabled and inrush
current is detected, there will be no tripping. Nevertheless, an annunciation is gener-
ated indicating that the time expired. Tripping signals and signals on the expiration of
time delay are available separately for each stage. The reset values are approximately
95 % below the pickup value for settings above I
N
. Lower values require a higher hys-
teresis in order to avoid intermittent pickup on currents near the pickup value
(e.g. 20 % at 0.2 ·I
N
).
Figures 2-67 and 2-68 show the logic diagrams for the overcurrent stages I> for
phase currents and for the zero sequence current stage3I0>.
To Next Page
Loading...
Need help?
General
