SmarAct METIRIO - Page 34

4 TECHNICAL DATA
Table 4.9: I
2
C Timing Specification
Parameter Symbol Test Conditions / Comments Min. Typ. Max. Unit
SCL
Frequency f
CLK
400 kHz
Minimum pulse width
High t
HIGH
0.6 µs
Low t
LOW
1.3 µs
Start condition S/Sr start / repeated start
Hold time t
HD−Start
first clock pulse hereafter 0.6 µs
Setup time t
SU−Start
0.6 µs
SDA setup
Hold time t
HD−Data
0 ns
Setup time t
SU−Data
100 ns
SCL and SDA 70 % to 30 %
Rise time t
r
300 ns
Fall time t
f
300 ns
Stop condition
Setup time t
SU−Stop
0.6 µs
Valid conditions
Data valid time t
VD−Data
0.9 µs
Acknowledge time t
VD−Ack
0.9 µs
Figure 4.9: I
2
C Timing scheme
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