Chapter 4 BIOS Setup
67
System BIOS
Cacheable
Selecting Enabled allows caching of the system
BIOS ROM at F0000h-FFFFFh, resulting in better
system performance.
SDRAM Cycle Time
Tras/Trc
Select the number of SCLKs for an access cycle.
The choices: 5/7; 7/9
SDRAM RAS-To-CAS
Delay
This field lets you insert a timing delay between the
CAS and RAS strobe signals, used when DRAM is
written to, read from, or refreshed. Fast gives faster
performance and Slow gives more stable
performance. This field applies only when synchronous
DRAM is installed in the system.
The Choices: 2; 3
SDRAM RAS
Precharge Time
If an insufficient number of cycles is allowed for the
RAS to accumulate its charge before DRAM refresh,
the refresh may be incomplete and the DRAM may
fail to retain data. Fast gives faster performance;
and Slow gives more stable performance. This field
applies only when synchronous DRAM is installed
in the system.
The Choices: 2; 3
SDRAM CAS Latency
Time
When synchronous DRAM is installed, the number
of clock cycles of CAS latency depends on the
DRAM timing. Do not reset this field from the default
value specified by the system designer.
Video BIOS Cacheable
Selecting Enabled allows caching of the system
BIOS ROM at C0000h to C7FFFh, resulting in video
performance. However, if any program writes to this
memory area, a system error may result.
Memory Hole At 15M-
16M
You can reserve this area of system memory for ISA
adapter ROM. When this area is reserved, it can-
not be cached. The user information of peripherals
that need to use this area of system memory usu-
ally discusses their memory requirements.
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