BIOS Setup
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P2C/C2P Concurrency This item allows you to enable/disable the PCI to
CPU, CPU to PCI concurrency.
The choices: Enabled; Disabled.
DRAM Clock The value represents the performance parameters
of the installed memory chips (DRAM). Do not
change the value from the factory setting unless you
install new memory that has a different performance
rating.
SDRAM Cycle Length Select CAS latency time in HCLKs of 2 or 3. The
system designer already set the values. Do not
change the default value unless you change speci-
fications of the installed DRAM or the installed CPU.
Memory Hole In order to improve performance, certain space in
memory is reserved for ISA cards. This memory must
be mapped into the memory space below 16MB.
The choices: 15M-16M; Disabled.
DRAM Timing By SPD When this item Enabled, DRAM Timing is set by
SPD.
SPD (Serial Presence Detect) is located on the
memory modules, BIOS reads information coded in
SPD during system boot up.
Bank Interleave
The choices: Disabled; 2 Bank; 4 Bank.
System BIOS
Cacheable
Selecting Enabled allows caching of the system
BIOS ROM at F0000h-FFFFFh, resulting in better
system performance.
Video RAM Cacheable Selecting Enabled allows caching of the video memory
(RAM) at A0000h-AFFFFh, resulting in better video
performance. However, check your AGP manual to
find out if any compatibility problem exists.
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