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SOLTEK SL-65KIV - Page 65

SOLTEK SL-65KIV
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BIOS Setup
65
CPU to PCI Write
Buffer
When this field is Enabled, writes from the CPU to
the PCI bus are buffered, to compensate for the
speed differences between the CPU and the PCI
bus. When Disabled, the writes are not buffered and
the CPU must wait until the write is complete before
starting another write cycle.
The choices: Enabled; Disabled.
PCI Dynamic Bursting When Enabled, every write transaction goes to the
write buffer. Bursting transactions then burst on the
PCI bus and non-bursting transactions don’t.
The choices: Enabled; Disabled.
PCI Master 0 WS Write When Enabled, writes to the PCI bus are executed
with zero wait states.
The choices: Enabled; Disabled.
PCI Delay Transaction Leave this field at default.
AGP Master 1 WS
Read
Leave this field at default.
AGP Master 1 WS
Write
Leave this field at default.
PCI # 2 Access # 1
Retry
The choices: Enabled; Disabled(default).
3. Press <ESC> to return to the Main Menu when you finish setting up all
items.
Memory Parity/ECC
Check
This item enabled to detect the memory parity and
Error Checking & Correcting.
The choices: Enabled; Disabled.

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