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Sony CDP-XE270 - IC Pin Function Description

Sony CDP-XE270
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22
CDP-XE270/XE370
6-8. IC PIN FUNCTION DESCRIPTION
Pin No. Pin Name I/O Description
1SQSOO
Subcode Q data output to the system controller (IC501)
2 SQCK I
Subcode Q data reading clock signal input from the system controller (IC501)
3 XRST I
System reset signal input from the system controller (IC501) “L”: reset
4 SYSM I
Analog line muting on/off control signal input terminal “H”: line muting on
Not used (fixed at “L”)
5DATAI
Serial data input from the system controller (IC501)
6 XLAT I
Serial data latch pulse signal input from the system controller (IC501)
7 CLOK I
Serial data transfer clock signal input from the system controller (IC501)
8 SENS O
Internal status (SENSE) output to the system controller (IC501)
9 SCLK I
SENSE serial data reading clock signal input from the system controller (IC501)
10 VDD
Power supply terminal (+5V) (digital system)
11 ATSK I/O
Input/output terminal for anti-shock Not used (pull down)
12 SPOA I
Microcomputer escape interface input A terminal Not used (fixed at “L”)
13 SPOB I
Microcomputer escape interface input B terminal Not used (fixed at “L”)
14 XLON O
Microcomputer escape interface output terminal Not used (open)
15 WFCK O
Write frame clock signal output terminal Not used (open)
16 XUGF O
XUGF signal output terminal Not used (open)
17 XPCK O
XPCK signal output terminal Not used (open)
18 GFS O
Guard frame sync signal output terminal Not used (open)
19 C2PO O
C2 pointer signal output terminal Not used (open)
20 SCOR O
Subcode sync (S0+S1) detection signal output to the system controller (IC501)
21 COUT I/O
Numbers of track counted signal input/output terminal Not used (open)
22 MIRR I/O
Mirror signal input/output terminal Not used (open)
23 DFCT I/O
Defect signal input/output terminal Not used (open)
24 FOK I/O
Focus OK signal input/output terminal Not used (open)
25 LOCK I/O
GFS is sampled by 460 Hz “H” when GFS is “H” Not used (open)
26 MDP O
Spindle motor (M101) servo drive signal output to the AN4800SB (IC150)
27 SSTP I
Detection signal input from limit in switch (S101)
The optical pick-up is inner position when “H”
28 SFDR O
Sled servo drive PWM signal (+) output to the AN4800SB (IC150)
29 SRDR O
Sled servo drive PWM signal (–) output to the AN4800SB (IC150)
30 TFDR O
Tracking servo drive PWM signal (+) output to the AN4800SB (IC150)
31 TRDR O
Tracking servo drive PWM signal (–) output to the AN4800SB (IC150)
32 FFDR O
Focus servo drive PWM signal (+) output to the AN4800SB (IC150)
33 FRDR O
Focus servo drive PWM signal (–) output to the AN4800SB (IC150)
34 VSS
Ground terminal (digital system)
35 TEST I
Input terminal for the test (fixed at “L”)
36 TES1 I
Input terminal for the test (fixed at “L”)
37 XTSL I
Input terminal for the system clock frequency setting
“L”: 16.9344 MHz, “H”: 33.8688 MHz (fixed at “L” in this set)
38 VC I
Middle point voltage (+2.5V) input from the CXA2581N (IC131)
39 FE I
Focus error signal input from the CXA2581N (IC131)
40 SE I
Sled error signal input from the CXA2581N (IC131)
41 TE I
Tracking error signal input from the CXA2581N (IC131)
42 CE I
Middle point servo analog signal input from the CXA2581N (IC131)
43 RFDC I
RF signal input from the CXA2581N (IC131)
BD BOARD IC101 CXD2587Q
(DIGITAL SIGNAL PROCESSOR, DIGITAL SERVO PROCESSOR, DIGITAL FILTER, D/A CONVERTER)

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