– 86 –
Pin No. Pin Name I/O Description
72 RREF I
Fix the video signal output level control
73 VREF O
Reference voltage (+1.235V) output terminal
74 AVDD-DAC —
Power supply terminal (+3.3V) (for D/A converter)
75 C-OUT O
Chrominance video signal output terminal
76 AGND-DAC —
Ground terminal (for D/A converter)
77 CLK-SEL0 I
GCK (pin `⁄‚fi) selection terminal “L”: external clock, “H”: internal clock (fixed at “H”)
78 CLK-SEL1 I
DA-XCLK (pin *§) selection (1) terminal Fixed at “H” in this set
79 CLK-SEL2 I
DA-XCLK (pin *§) selection (2) terminal Fixed at “H” in this set
80 VSS —
Ground terminal
81 RESERVED I
Selection the operation clock 42.336 MHz (fixed at “L”)
82 VDD3 —
Power supply terminal (+3.3V)
83 DA-EMP O
Not used (open)
84 RESERVED O
Not used (open)
85 AGND-PLL —
Ground terminal (for PLL system)
86 DA-XCLK I
Main reference clock signal (16.9344 MHz=384fs) from the D/A converter (IC509)
87 AVDD-PLL —
Power supply terminal (+3.3V) (for PLL system)
88 PGIO4 I/O
Not used (open)
89 PGIO5 I/O
Not used (open)
90 PGIO6 I/O
Not used (open)
91 PGIO0 I/O
Not used (open)
92 PGIO8 I/O
Not used (open)
93
PGIO2/VSYNC/
CSYNC
O
Vertical synchronized signal output to the CD mechanism controller (IC502)
94 AVDD-PLL —
Power supply terminal (+3.3V) (for PLL system)
95 to 97 NC O
Not used (open)
98 AGND-PLL —
Ground terminal (for PLL system)
99 VSS —
Ground terminal
100 NC O
Not used (open)
101
PGIO3/HSYNC
I/O
Not used (open)
102 VDD3 —
Power supply terminal (+3.3V)
103
PGIO1/VCK-OUT
I/O
Not used (open)
104 VSS —
Ground terminal
105 GCK I
Not used (open)
106 VCK-IN I
Main clock for video signal processor input from the D/A converter (IC509) (27 MHz)
107
GCKOUT/DA-EMP
O
Not used (open)
108 DA-LRCK O
Digital audio L/R sampling clock signal (44.1 kHz) output to the D/A converter (IC509)
109 VDDMAX-OUT O
Fix the maximum output voltage (+5V) certain output terminal
110 DA-DATA O
Digital audio data output to the D/A converter (IC509)
111 DA-BCK O
Digital audio bit clock signal (2.8224 MHz) output to the D/A converter (IC509)
112 HD-OUT O
Serial data output to the CD mechanism controller (IC502)
113 HRDY O
Ready signal output to the CD mechanism controller (IC502)
114 HINT O
Interrupt request signal output to the CD mechanism controller (IC502)
115 CDG-SCK I/O
Not used (open)
116 VSS —
Ground terminal
117 HCK I
Serial data transfer clock signal input from the CD mechanism controller (IC502)
118 VDD3 —
Power supply terminal (+3.3V)
119 HD-IN I
Serial data input from the CD mechanism controller (IC502)
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TEL 13942296513 QQ 376315150 892498299
TEL 13942296513 QQ 376315150 892498299
http://www.xiaoyu163.com
http://www.xiaoyu163.com
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