PCM-D50
56
Pin No.Pin NameI/O Description
K23LCD_ENABLE — Not used (Open)
K24LCD_VSYNC — Not used (Open)
K25 CHGGND2 — Ground
K26 CHG — Not used (Open)
L1SDR_DATA23OLED drive signal output
L2SDR_DATA22OLED drive signal output
L3SDR_DATA21OLED drive signal output
L4SDR_DATA20 — Not used (Open)
L5SDR_DATA24OLED drive signal output
L8SDR_DATA19 — Not used (Open)
L9 NAND_DA4I/OData input/output with the NAND ROM
L10 GND — Ground
L11 NC — Not used (Open)
L17, L18 GND — Ground
L19,
L22 to L25
LCD_B1 to LCD_B5 — Not used (Open)
L26 BSEN — Not used (Open)
M1 to M3
SDR_DATA18 to
SDR_DATA16
— Not used (Open)
M4, M5
SDR_DATA15,
SDR_DATA14
I/OData input/output with SD-RAM
M8SDR_DATA13I/OData input/output with SD-RAM
M9NAND_CSZ0OChip enable signal output to the NAND ROM
M10, M17,
M18
GND — Ground
M19 LCD_B0 — Not used (Open)
M22 to M25
LCD_G0 to LCD_G3 — Not used (Open)
M26VL0ONot used (Open)
N1 to N5
SDR_DATA12 to
SDR_DATA8
I/OData input/output with SD-RAM
N8SDR_DATA7I/OData input/output with SD-RAM
N9, N10,
N17 to N19
GND — Ground
N22, N23LCD_G4, LCD_G5 — Not used (Open)
N24, N25LCD_R0, LCD_R1 — Not used (Open)
N26 VMICIN IPower supply (+3.3V)
P1 to P4
SDR_DATA5 to
SDR_DATA2
I/OData input/output with SD-RAM
P5 SDR_DQM0OWrite mask signal output to SD-RAM
P8 SDR_DATA6I/OData input/output with SD-RAM
P9 GND — Ground
P10 RESETZOReset signal output (Not used in this set)
P17 to P19GND — Ground
P22 LCD_R3 — Not used (Open)
P23LCD_PXCLK — Not used (Open)
P24 ID — Not used (Open)
P25, P26 IO_A — Power supply (VDD_GP1)
R1SDR_DATA0I/OData input/output with SD-RAM
R2, R3
SDR_DQM3,
SDR_DQM2
O
Write mask signal output to SD-RAM
(Not used in this set) (Open)
R4 SDR_DQM1OWrite mask signal output to SD-RAM
R5 SDR_WEZOWrite enable signal output to SD-RAM
R8SDR_DATA1I/OData input/output with SD-RAM
R9 GND — Ground
R10 MWI_SI — Not used (Open)
R17, R18U70_CTSZ, U70_RTSZ — Not used (Open)
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