38
STR-DB900
Pin No. Pin Name I/O Description
50 PAGE2 O Not used. (Open)
51 VSS — Ground
52, 53 PAGE1, PAGE0 O Not used. (Open)
54 BOOT I Not used. (Connected to ground.)
55 TST1 I Not used. (Open)
56 BST I Boot strap signal input
57 MOD1 I Operation mode setting pin Connected to VDD
58 MOD0 I Operation mode setting pin Connected to ground
59 EXLOCK I PLL lock error signal and data error flag input
60 VDDI — Power supply (+2.5 V)
61 VSS — Ground
62, 63 A17, A16 O Address signal output Not used. (Open)
64 to 66 A15 to A13 O Address signal output to DRAM
67 GP10 — Not used. (Open)
68 GP9 I/O Audio signal input/output to MB91354APMT
69 GP8 I Channel status bit 1 input from LC89056W
70 VDDI — Power supply (+2.5 V)
71 VSS — Ground
72 to 75 D15/GP7 to D12/GP4 I/O DRAM data input/output
76 VDDE — Power supply (+3.3 V)
77 to 80 D11/GP3 to D8/GP0 I/O DRAM data input/output
81 VSS — Ground
82 to 85 A9, A12 to A10 O Address signal output to DRAM
86 TDO O Not used. (Open)
87 TMS I Not used. (Open)
88 XTRST I Not used. (Open)
89 TCK I Not used. (Open)
90 TDI I Not used. (Open)
91 VSS — Ground
92 to 97 A8 to A3 O Address signal output to DRAM
98, 99 D7, D6 I/O DRAM data input/output
100 VDDI — Power supply (+2.5 V)
101 VSS — Ground
102 to 105 D5 to D2 I/O DRAM data input/output
106 VDDE — Power supply (+3.3 V)
107, 108 D1, D0 I/O DRAM data input/output
109, 110 A2, A1 O Address signal output to DRAM
111 VSS — Ground
112 A0 O Address signal output to DRAM
113 PM I PM signal input from MB91354APMT
114 SDI3 I Audio serial data input
115 SDI4 I Not used. (Connected to ground.)
116 SYNC I Sync/non-sync setting pin (“L”: sync, “H”: non-sync) Connected to VDD
117 TST2 — Not used. (Connected to ground.)
118 GP11 — Not used. (Open)
119 TST3 — Not used. (Connected to ground.)
120 VDDI — Power supply (+2.5 V)
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