Table 100. FSMC_SM_2
SM CODE FSMC_SM_2
Description Periodical read-back of FSMC configuration registers
Ownership End user
Detailed implementation
This method must be applied to FSMC configuration registers.
Detailed information on the implementation of this method can be found in Section 3.6.5
Error reporting Refer to NVIC_SM_0
Fault detection time Refer to NVIC_SM_0
Addressed fault model Refer to NVIC_SM_0
Dependency on MCU configuration FSMC interface is available only on selected part numbers
Initialization Refer to NVIC_SM_0
Periodicity Refer to NVIC_SM_0
Test for the diagnostic Refer to NVIC_SM_0
Multiple faults protection Refer to NVIC_SM_0
Recommendations and known limitations Refer to NVIC_SM_0
Table 101. FSMC_SM_3
SM CODE FSMC_SM_3
Description ECC engine on NAND interface in FSMC module
Ownership ST
Detailed implementation
The FMC NAND Card controller includes two error correction code computation hardware blocks,
one per memory bank. They reduce the host CPU workload when processing the ECC by software.
ECC mechanism protects data integrity on the external memory connected to NAND port
Error reporting Refer to functional documentation
Fault detection time ECC bits are checked during a memory reading
Addressed fault model Permanent and Transient
Dependency on MCU configuration FSMC interface is available only on selected part numbers
Initialization None
Periodicity Continuous
Test for the diagnostic Not needed
Multiple faults protection FSMC_SM_2: Periodical read-back of FSMC configuration registers
Recommendations and known
limitations
This method has negligible efficiency in detecting hardware random failures affecting the FSMC
interface. It can be part of End user safety concept because addressing memories outside
STM32F2 Series MCU
UM1845
Description of hardware and software diagnostics
UM1845 - Rev 4
page 68/108
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