3.6.19 Reset and clock control (RCC) subsystem
Table 85. CLK_SM_0
SM CODE CLK_SM_0
Description Periodical read-back of configuration registers
Ownership End user
Detailed implementation
This method must be applied to configuration registers for clock and reset system (refer to RCC
register map).
Detailed information on the implementation of this method can be found in Section 3.6.5
Error reporting Refer to NVIC_SM_0
Fault detection time Refer to NVIC_SM_0
Addressed fault model Refer to NVIC_SM_0
Dependency on MCU configuration Refer to NVIC_SM_0
Initialization Refer to NVIC_SM_0
Periodicity Refer to NVIC_SM_0
Test for the diagnostic Refer to NVIC_SM_0
Multiple faults protection Refer to NVIC_SM_0
Recommendations and known limitations Refer to NVIC_SM_0
Table 86. CLK_SM_1
SM CODE CLK_SM_1
Description Clock security system (CSS)
Ownership ST
Detailed implementation
The clock security system (CSS) detects the loss of HSE clock activity and executes the
corresponding recovery action, such as:
• Switch-off HSE
• Commutation on the HIS
• Generation of related NMI
Error reporting NMI
Fault detection time Depends on implementation (clock frequency value)
Addressed fault model Permanent and Transient
Dependency on MCU configuration None
Initialization CSS protection must be enabled on Clock interrupt register (RCC_CIR) after boot stabilization
Periodicity Continuous
Test for the diagnostic CLK_SM_0: periodical read-back of configuration registers
Multiple faults protection CPU_SM_5: external watchdog
Recommendations and known limitations
It is recommended to carefully read Reference Manual instruction on NMI generation, in order to
correct managing the faulty situation by application software features
Table 87. CLK_SM_2
SM CODE CLK_SM_2
Description Independent watchdog
UM1845
Description of hardware and software diagnostics
UM1845 - Rev 4
page 59/108
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