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Reference design AN4938

36/48 DocID029918 Rev 1

VSS - 51M861 72 F2

VDD - 52 N8 62 73 H5

VSS -----G7

VDD -----H13

VSS - 61M971 82G8

VDD - 62 N9 72 83 J13

VSS -----G9

VDD - - - - - K5

VCAP1 48 71 M10 81 92 U11

VSS 49 - - - 93 G10

VDDLDO1 - - - - - U12

VDD - 72 N10 82 94 K13

VDD33 USB50-----

VSS -----G11

VDD -----L5

VSS - - H12 90 - H7

VDD - - J12 91 103 L13

VDD -----M5

VSS -----H8

VSS - 83 - 102 114 H9

VDD - 84 J13 103 115 M13

VDD -----N7

VSS -----H10

VDD - - - - 124 N8

VDD -----N10

VSS ----125H11

VDD -----N11

VSS -----J7

VDD -----N12

VSS -----J8

Table 9. Reference connection for all packages (continued)

Pin name (function

after reset)

Pin/ball name

LQFP100

LQFP144

UFBGA176+25

LQFP176

LQFP208

TFBGA240+25

Table of Contents2
Power Supplies7
Introduction7
Independent Analog Supply and Reference Voltage7
USB Transceiver Independent Power Supply7
Figure 1. VDD33USB Connected to VDD Power Supply8
Figure 2. VDD33USB Connected to External Power Supply9
Figure 3. VDD50USB Power Supply9
Battery Backup Domain10
LDO Voltage Regulator10
Power Supply Scheme11
Figure 4. Power Supply Overview12
Reset and Power Supply Supervisor13
Power-On Reset (Por)/Power-Down Reset (PDR)13
Programmable Voltage Detector (PVD)13
Figure 5. Power on Reset/Power down Reset Waveform13
Analog Voltage Detector (AVD)14
System Reset14
Figure 6. PVD Threshold14
Internal Reset on15
Internal Reset off15
Figure 7. Reset Circuit15
Figure 8. Power Supply Supervisor Interconnection with Internal Reset off16
Bypass Mode17
Figure 9. NRST Circuitry Timing Example17
Alternate Function Mapping to Pins18
Figure 10. Stm32Cubemx Example Screen-Shot18
Clocks19
HSE Oscillator Clock19
Figure 11. HSE External Clock19
Figure 12. HSE Crystal/Ceramic Resonators19
External User Clock (HSE Bypass)20
External Crystal/Ceramic Resonator (HSE Crystal)20
LSE Oscillator Clock20
External Clock (LSE Bypass)21
External Crystal/Ceramic Resonator (LSE Crystal)21
Figure 13. LSE External Clock21
Figure 14. LSE Crystal/Ceramic Resonators21
Clock Security System (CSS)22
Boot Configuration23
Boot Mode Selection23
Table 1. Boot Modes23
Boot Pin Connection24
System Bootloader Mode24
Table 2. Stm32H743/753Xx Bootloader Communication Peripherals24
Figure 15. Boot Mode Selection Implementation Example24
Debug Management26
Introduction26
SWJ Debug Port (Serial Wire and JTAG)26
TPIU Trace Port26
Figure 16. Host to Board Connection26
External Debug Trigger27
Pinout and Debug Port Pins27
SWJ Debug Port Pins27
Table 3. TPIU Trace Pins27
Table 4. External Debug Trigger Pins27
Flexible SWJ-DP Pin Assignment28
Table 5. SWJ Debug Port Pins28
Table 6. Flexible SWJ-DP Assignment28
Internal Pull-Up and Pull-Down on JTAG Pins29
SWJ Debug Port Connection with Standard JTAG Connector29
Figure 17. JTAG Connector Implementation29
Recommendations30
Printed Circuit Board30
Component Position30
Ground and Power Supply (VSS,VDD)30
Decoupling30
Other Signals31
Unused I/Os and Features31
Figure 18. Typical Layout for VDD/VSS Pair31
Reference Design32
Description32
Clocks32
Reset32
Boot Mode32
SWJ Interface32
Power Supply32
Component References32
Table 7. Mandatory Components32
Table 8. Optional Components33
Figure 19. STM32H753XI Reference Schematic34
Table 9. Reference Connection for All Packages35
Recommended PCB Routing Guidelines for Stm32H743/753Xx Devices39
PCB Stack-Up39
Figure 20. Four Layer PCB Stack-Up Example39
Crystal Oscillator40
Power Supply Decoupling40
Figure 21. Six Layer PCB Stack-Up Example40
Figure 22. Decoupling Capacitor Placement Depending on Package Type41
Figure 23. Example of Decoupling Capacitor Placed Underneath the Stm32H743/753Xx41
High Speed Signal Layout42
SDMMC Bus Interface42
Flexible Memory Controller (FMC) Interface42
Quadrature Serial Parallel Interface (QUADSPI)43
Embedded Trace Macrocell (ETM)45
Table 10. Document Revision History47

Brand	ST
Model	STM32H7 3 Series
Category	Microcontrollers
Language	English

ST STM32H7 3 Series User Manual

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