Recommended PCB routing guidelines for STM32H743/753xx devices AN4938
44/48 DocID029918 Rev 1
Interface signal layout guidelines
• Reference the plane using GND or PWR (if PWR, add 10nf stitching cap between PWR
and GND
• Trace the impedance: 50 W ± 10%
• The maximum trace length should be below 120mm. If the signal trace exceeds this
trace-length/speed criterion, then a termination should be used
• Avoid using multiple signal layers for the data signal routing.
• Route the clock signal at least 3x of the trace away from other signals. Use as less vias
as possible to avoid the impedance change and reflection. Avoid using a serpentine
routing.
• Match the trace lengths for the data group within ± 10 mm of each other to diminish
skew. Serpentine traces (back and forth traces in an “S” pattern to increase trace
length) can be used to match the lengths.
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