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ST STM32H74xI/G User Manual
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AN4938 Rev 4
27/46
AN4938
Boot configuration
45
SPI3
PC12/PC1
1/PC10/P
A15
SPI4
PE1
1 / PE12 / PE13 / PE14
USB OTG_FS in Device mode
(DFU)
P
A1
1/P
A12
T
able 3. STM32H74xI/G and STM32H
75xI
/G bootloader communication per
ipherals
Bootloader p
eripherals
Bootloader pin
s
26
28
Table of Contents
Default Chapter
2
Table of Contents
2
General Information
7
Power Supplies
7
Introduction
7
Independent Analog Supply and Reference Voltage
7
USB Transceiver Independent Power Supply
8
Figure 1. VDD33USB Connected to VDD Power Supply
9
Battery Backup Domain
10
LDO Voltage Regulator
10
SMPS Step-Down Converter
11
Power Supply Scheme
12
Figure 3. Power Supply Overview
14
Reset and Power Supply Supervisor
15
Power-On Reset (Por)/Power-Down Reset (PDR)
15
Programmable Voltage Detector (PVD)
15
Figure 4. Power on Reset/Power down Reset Waveform
15
Analog Voltage Detector (AVD)
16
System Reset
16
Figure 5. PVD Threshold
16
Internal Reset on
17
Internal Reset off
17
Figure 6. Reset Circuit
17
Figure 7. Power Supply Supervisor Interconnection with Internal Reset off
18
Bypass Mode
19
Figure 8. NRST Circuitry Timing Example
19
Alternate Function Mapping to Pins
20
Figure 9. Stm32Cubemx Example Screen-Shot
20
Clocks
21
HSE Oscillator Clock
21
Figure 10. HSE External Clock
21
Figure 11. HSE Crystal/Ceramic Resonators
21
External Crystal/Ceramic Resonator (HSE Crystal)
22
External User Clock (HSE Bypass)
22
LSE Oscillator Clock
22
External Clock (LSE Bypass)
23
External Crystal/Ceramic Resonator (LSE Crystal)
23
Figure 12. LSE External Clock
23
Figure 13. LSE Crystal/Ceramic Resonators
23
Clock Security System (CSS)
24
Boot Configuration
25
Boot Mode Selection
25
Table 2. Boot Modes
25
Boot Pin Connection
26
System Bootloader Mode
26
Table 3. Stm32H74Xi/G and Stm32H75Xi/G Bootloader Communication Peripherals
26
Figure 14. Boot Mode Selection Implementation Example
26
Debug Management
28
Introduction
28
SWJ Debug Port (Serial Wire and JTAG)
28
TPIU Trace Port
28
Figure 15. Host to Board Connection
28
External Debug Trigger
29
Pinout and Debug Port Pins
29
SWJ Debug Port Pins
29
Table 4. TPIU Trace Pins
29
Table 5. External Debug Trigger Pins
29
Flexible SWJ-DP Pin Assignment
30
Table 6. SWJ Debug Port Pins
30
Table 7. Flexible SWJ-DP Assignment
30
Internal Pull-Up and Pull-Down on JTAG Pins
31
SWJ Debug Port Connection with Standard JTAG Connector
31
Figure 16. JTAG Connector Implementation
31
Recommendations
32
Printed Circuit Board
32
Component Position
32
Ground and Power Supply (VSS,VDD)
32
Decoupling
32
Other Signals
33
Unused I/Os and Features
33
Figure 17. Typical Layout for VDD/VSS Pair
33
Reference Design
34
Reference Design Description
34
Clocks
34
Reset
34
Boot Mode
34
SWJ Interface
34
Power Supply
34
Component References
35
Table 8. Mandatory Components
35
Table 9. Optional Components
35
Figure 18. STM32H753XI Reference Schematic
36
Recommended PCB Routing Guidelines for Stm32H74Xi/G and Stm32H75Xi/G Devices
37
PCB Stack-Up
37
Figure 19. Four Layer PCB Stack-Up Example
37
Crystal Oscillator
38
Power Supply Decoupling
38
Figure 20. Six Layer PCB Stack-Up Example
38
Figure 21. Decoupling Capacitor Placement Depending on Package Type
39
Figure 22. Example of Decoupling Capacitor Placed Underneath
39
The Stm32H74Xi/G and Stm32H75Xi/G
39
High Speed Signal Layout
40
SDMMC Bus Interface
40
Flexible Memory Controller (FMC) Interface
40
Quadrature Serial Parallel Interface (QUADSPI)
41
Embedded Trace Macrocell (ETM)
43
Conclusion
44
Revision History
45
Table 1. Applicable Products
45
Table 10. Document Revision History
45
Figure 2. VDD33USB/VDD50USB Connected to External Power Supply
45
4
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ST STM32H74xI/G Specifications
General
Brand
ST
Model
STM32H74xI/G
Category
Microcontrollers
Language
English
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