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Chapter 3: Maintenance and Component Installation
Symmetric Population within one CPU
Modes
P1/P2-
DIMMF1
P1/P2-
DIMME1
P1/P2-
DIMMD1
P1/P2-
DIMMA1
P1/P2-
DIMMB1
P1/P2-
DIMMC1
ChannelCong.
AD DCPMM DRAM1 DRAM1 DRAM1 DRAM1 DCPMM 1-1-1
MM DCPMM DRAM1 DRAM1 DRAM1 DRAM1 DCPMM 1-1-1
AD +
MM
DCPMM DRAM3 DRAM3 DRAM3 DRAM3 DCPMM 1-1-1
AD: App Direct, MM: Memory Mode
Legend (for the table above)
DDR4 Type Capacity
DRAM1 RDIMM 3DS RDIMM LRDIMM 3DS LRDIMM Any Capacity
DRAM2 RDIMM - -
Refer to Validation Matrix below.
DRAM3 RDIMM 3DS RDIMM LRDIMM -
Note: DDR4 single rank x8 is not available for DCPMM Memory Mode or App-Direct Mode.
Validation Matrix (DDR4 DIMMs Validated w/DCPMM)
DIMM Type
Ranks Per DIMM
& Data Width
(Stack)
DIMM Capacity (GB)
DRAM Density
4Gb 8Gb
RDIMM
1Rx4 8GB 16GB
2Rx8 8GB 16GB
2Rx4 16GB 32GB
LRDIMM 4Rx4 N/A 64GB
LRDIMM 3DS 8Rx4 (4H) N/A 128GB
• For MM, general NM/FM ratio is between 1:4 and 1:16. Excessive capacity for FM can
be used for AD. (NM = Near Memory; FM = Far Memory)
• For each individual population, rearrangements between channels are allowed as long
as the resulting population is compliant with the PDG rules for the 82xx/62xx/52xx/42xx
platform.
• For each individual population, please use the same DDR4 DIMM in all slots.
• For each individual population, sockets are normally symmetric with exceptions for 1
DCPMM per socket and 1 DCPMM per node case. Currently, DCPMM modules oper-
ate at 2666 MHz.
• No mixing of DCPMM and NVMDIMMs within the same platform is allowed.
• This DCPMM population guide targets a balanced DCPMM-to-DRAM-cache ratio in MM
and MM + AD modes.
DCPMM Population for 2nd Gen Scalable Processors (82xx/62xx/52xx/42xx)
Only 2nd Gen Scalable Processors support DCPMM modules.