Chapter 7: AMI BIOS
7-7
CPU C-State
C-States architecture, a processor power management platform developed by
Intel, can further reduce power consumption from the basic C1 (Halt State) state
that blocks clock cycles to the CPU. Select Enabled for CPU C-Sates support. The
options are Enabled and Disabled. If this feature is set to Enabled, the following
items will display:
Enhanced Halt State (C1E) (Available when "CPU C-States" is set to
Enabled)
Select Enabled to support Enhanced C1 Power State to boost system performance.
Dis-
abled and Enabled.
ACPI C2 (Available when "CPU C-States" is set to Enabled)
Select Enabled for ACPI C2 support to determine how the processor will report the
CPU-C state to the operating system. The options are Disabled, C6 NS, and C6 FS.
Monitor/Mwait
Select Enabled to implement the Mwait instruction along with the Monitor instruction
to allow the processor to specify the location for the BIOS to monitor activities and
to issue the instruction to put the operation on hold (Mwait).
L1 Prefetcher (Available when supported by the CPU)
If enabled, the hardware prefetcher will prefetch streams of data and instructions
from the main memory to the L1 cache to improve CPU performance. The options
are Disabled and Enabled.
L2 Prefetcher (Available when supported by the CPU)
If enabled, the hardware prefetcher will prefetch streams of data and instructions
from the main memory to the L2 cache to improve CPU performance. The options
are Disabled and Enabled.
ACPI 3.0 T-States (Available when "CPU C-States" is set to Enabled)
T-States to determine how the processor will report to the operating system during
CPU-Throttling states. The options are Enabled and Disabled.
Fast String
Select Enabled to enable Fast String support for REP MOVS/STOS, which will carry
out Repeat-String Operation instructions to move a string of commands to another
location (MOVS) or to add a string of commands to an existing instruction code
(STOS). The options are Disabled and Enabled.
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