Synopsys TSMC180 - 11 Cell Routing Constrains; Power and Reference Routing; Analog Input Routing

DWC ADC 12b5M SAR, TSMC180 IP Databook
April 2012 Synopsys, Inc. 25-30
11 Cell Routing Constrains
The table below presents the signals whose routing must follow constrains.
Unless otherwise stated the analog signal shielding is made with each cell‟s agnd (or avdd
as 2
nd
option).
Table 4 – ADC signals with routing constrains
Cell Pin Name
Wire
Resistance
[ohm]
Wire Current
[mA]
Recommendation
Power
avdd
<10
>1
For full performance, the supply voltage at the boundary of the IP
must respect the range in databook‟s specification table.
agnd
<1
>1
n.a.
dvdd
<10
<.1
For full performance, the supply voltage at the boundary of the IP
must respect the range in databook‟s specification table.
dgnd
<1
<0.1
n.a.
References and Bias
vrefp
<10
<0.1
Shield from any digital signal.
Higher wire resistance increases the gain error.
agndref
<10
<0.1
Shield from any digital signal.
Higher wire resistance increases the offset error.
dvdd_ldo
<10
>1
Load capacitance should be below 5pF
Input Signals
vinpXvinnX
<50
n.a.
Shield from any digital signal and other vinX
Different routing between inputs may originate gain and offset
errors between channels
n.a. – Not Applicable