Synopsys TSMC180 - Table of Contents

DWC ADC 12b5M SAR, TSMC180 IP Databook
April 2012 Synopsys, Inc. 3-30
Contents
1 Features............................................................................................................................... 4
2 General Description ............................................................................................................ 4
3 Functional Diagram ............................................................................................................ 4
4 Specifications ...................................................................................................................... 5
5 Pin Description ................................................................................................................... 8
6 Operating Modes .............................................................................................................. 10
Start-Up Sequence ................................................................................................................ 10
Deep power down mode ..................................................................................................... 11
Power-down Mode .............................................................................................................. 11
Standby Mode ...................................................................................................................... 12
Normal Operation ................................................................................................................ 12
Current Consumption during Normal Operation............................................................... 12
Internal Voltage Regulator................................................................................................... 13
7 Timing Diagrams .............................................................................................................. 14
8 Digital Offset Calibration ................................................................................................. 19
10 Application Notes ......................................................................................................... 23
Cell Placement...................................................................................................................... 23
Power Supplies .................................................................................................................... 23
System Level Clock Issues ................................................................................................... 24
Routing of Analog and Reference Signals ........................................................................... 24
ESD / Latch-Up ................................................................................................................... 24
11 Cell Routing Constrains................................................................................................ 25
12 Connections to the IO PAD ring ................................................................................... 26
13 PCB Guidelines ............................................................................................................. 29
Appendix A – Minimum Sampling Time – (Worst case conditions) ...................................... 30